QT2022/32 - Data Sheet: DS3051
11 Diagnostic and Test Features
11.1 Loopback Modes
Table 39: System Loopback Modes and MDIO Control Registers
Loopback
Enable
Loopback Data
Override
TXOUT output when data
override=0 (default)1
TXOUT output when data
override=1
Loopback name
PMA system loopback
1.0.0
1.C001h.15
2.C001h.4
all 0’s (null)
0F0F
transmit data
transmit data
WIS system loopback
(QT2032 only) 2
2.0.14
PCS system loopback
XGXS system loopback
XGXS analog loopback
3.0.14
3.C000h.5
4.C000h.15
n/a
00FF
all 1’s
n/a
transmit data
transmit data
transmit data
4.C000h.14
4.C007h.3:0
1.
2.
The Loopback Data Override bits are set to 0 by default for all system loopbacks
The WIS system loopback feature is available on the QT2032 product only.
When in any system (PMA, PCS or XGXS system) loopback mode the QT2022/32 shall accept data from the
transmit path and return it on the receive path. During PMA system loopback, the PMA transmit data will default to
an all 0’s pattern at TXOUTP/N. During XGXS system loopback, the PMA transmit data will default to an all 1’s pat-
tern at TXOUTP/N. In PCS or WIS system loopback mode a continuous pattern of 0x00FF will be output. In all
modes, transmit data will be output if the associated ‘loopback data out enable bit’ is set high for the enabled loop-
back mode. .
Table 40: Network Loopback Modes and MDIO Control Registers
Loopback
Enable
Loopback Data
Override
RxXAUI output when data
override=0
RxXAUI output when data
override=1 (default)1
Loopback name
XGXS network loopback
PMA network loopback
4.0.14
4.C000h.13
1.C001h.5
all 0’s
received data
received data
1.C001h.4
idle at RxXAUI
1.
The Loopback Data Override bits are set to 1 by default for all network loopbacks
When in PMA network loopback mode, the recovered and retimed 10Gb/s data is looped to the transmitter output
driver and output at TXOUTP/N. The clock output at TXPLLOUTP/N is still synchronous to the Tx path PLL 10GHz
clock. To lock the Tx PLL to the receive data, use line timing mode. The receive path XAUI output data will be
received data. XAUI idle codes will be output instead of the received data if the ‘network loopback data out enable
bit’ is set high. In IEEE 802.3 standard XGXS network loopback the recovered received data is looped back to the
transmit path in the XAUI block.
The chip will not prevent multiple loopbacks from being enabled but the result is undefined and these modes are
not supported.
11.1.1 XGXS Analog Loopback
The signal from any of the four TxXAUI CDRs can be looped back to the RxXAUI3 output by setting 4.C007h.2=1
and selecting the lane via 4.C007h.1:0. By default, the recovered data is output. The recovered clock can be output
instead by setting 4.C007h.3=1.
96
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