QT2022/32 - Data Sheet: DS3051
Figure 37: MDIO Register Indirect Access Memory Mapping for I2C Access
2-Wire Serial Address
0111111x (7Eh)
0-
123
Command status register:
bit 7 - 2: Reserved
bit 1: 1 = Chip write command fail
0 = Chip write command pass
(RO/LH)
124
bit 0: 1 = MDIO read command fail
0 = MDIO read command pass
(RO/LH)
125
126
127
Device ID[7:0]
Register Address[15:8]
Register Address[7:0]
MDIO Register Data[15:8] for
128 Device ID[7:0]
Register Address[15:0]
MDIO Addr0
MDIO Register Data[7:0] for
Device ID[7:0]
129
130
Register Address[15:0]
MDIO Register Data[15:8] for
Device ID[7:0]
Register Address[15:0] + 1
MDIO Addr1
MDIO Register Data[7:0] for
Device ID[7:0]
Register Address[15:0] + 1
131
132
253
...
MDIO Register Data[15:8] for
254 Device ID[7:0]
Register Address[15:0] + 63
MDIO Addr63
MDIO Register Data[7:0] for
Device ID[7:0]
Register Address[15:0] + 63
255
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