QT2022/32 - Data Sheet: DS3051
Table 3: QT2022/32 Ball Assignment & Signal Description (Continued)
Ball
Signal Name
Dir.
Type
Description
C3
TXFAULT
(XFPMODNR)
I
CMOS with 50kΩ
pullup to 1.2V
With XFP=0, External laser or laser-driver fault indicator as per XENPAK
MSA
logic low = normal operation
logic high = fault condition
(See “Laser Driver Enable Pin (TXENABLE)” on page 69.)
With XFP=1, high level indicates XFP module not ready
E2
E1
C1
B1
A1
PRTAD<0>
PRTAD<1>
PRTAD<2>
PRTAD<3>
PRTAD<4>
I
I
CMOS
no pullup or pulldown
Port address for MDIO transactions. See “Management Frame Format” on
page 74. for more information on the MDIO/C interface.
C11
RESETN
CMOS with
hysteresis
reset, active low
logic low = reset condition
25kΩ pullup
logic high = normal operation
Note: the TAP port controller is only reset by the TRST_N pin and is
unaffected by RESETN
Note: in a module application XFP=0 & the external cap for the powerup
reset must be connected to the TRST_N input. For further details, please
see Section 18.5 on page 210
CMOS
Test pins for Test Access Port (or internal scan testing when SCAN
instruction written to TAP).
D6
D3
G3
TDI
TCK
TRST_N
I
I
I
36kΩ pullup
(no pullup/dn)
25kΩ pullup
Test data input (scan in)
Test clock input (scan clock)
Test reset, active low (hold high for scan)
with XFP=0, also resets the core and is to be used as the connection
point for an external cap to GND for a powerup reset.
Test mode select, active low (hold high for scan)
E7
TMS
I
36kΩ pullup
CMOS Outputs (note: all CMOS outputs are 3.3V tolerant open drain)
E12
LTIMEOK
O
CMOS open drain
(see note1)
QT2032:
Line-timing internal enable indication.
logic high = conditions are valid for line-timing operation and it is internally
enabled.
A low level can be used to center the external VXCO in a VXCO-only
application.
(see Section 6.2.4, “VCXO PLL,” on page 32 for a description of the logic)
QT2022:
Unused. Connect to GND.
E10
E11
RDCC
O
O
CMOS open drain
(see note1)
QT2032:
Receive data communication channel output for both section and line
SONET overhead data; timed from the RDCC_CLK clock output. Please
see Section 7.3.8, “Transport Overhead Serial Interface,” on page 48.
QT2022:
Unused. Connect to GND.
RDCC_CLK
CMOS open drain
(see note1)
QT2032:
Gapped clock used for timing RDCC output.
Please see Section 7.3.8, “Transport Overhead Serial Interface,” on
page 48.
QT2022:
Unused. Connect to GND.
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