QT2022/32 - Data Sheet: DS3051
PCS Vendor Specific
Packet Generator Send
Data MSB
PCS Vendor Specific
Packet Generator Send
Data LSB
PCS Vendor Specific
Packet Generator Send
Control
PCS Vendor Specific
Packet Generator Control
3.C020
Bit
3.C021
3.C022
3.C023
TX Packet Generator Enable 1,
RW
0 = Disable, Default
1 = Enable
0
Lane 2 XGMII Data Byte, RW
Default = 8’h00
Lane 0 XGMII Data Byte, RW
Default = 8’h00
Lane 0 XGMII Control Bit, RW
0 = Data, Default
1 = Control
RX Packet Generator Enable 1,
RW
0 = Disable, Default
1 = Enable
1
Lane 1 XGMII Control Bit, RW
0 = Data, Default
1 = Control
2
3
Reserved, RO
Reserved, RO
Lane 2 XGMII Control Bit, RW
0 = Data, Default
1 = Control
Lane 3 XGMII Control Bit, RW
0 = Data, Default
1 = Control
4
5
Packet Type, RW
00 = Data (fixed)
01 = Data (incremental)
10 = Control (fixed)
11 = Reserved
Reserved, RO
Reserved, RO
Default = 00
6
7
8
9
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Generator Mode, RW
00 = Idle Mode
01 = Burst Mode
10 = Continuous Mode
11 = Reserved
Lane 3 XGMII Data Byte, RW
Default = 8’h00
Lane 1 XGMII Data Byte, RW
Default = 8’h00
Default = 00
10
11
12
13
14
15
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
1. When either packet generator is enabled, both Tx and Rx packet checkers will be automatically enabled.
170
AppliedMicro - Confidential & Proprietary
Revision 5.11
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
