QT2022/32 - Data Sheet: DS3051
PCS Vendor Specific
Packet Generator
Burst Size
PCS Vendor Specific
Packet Generator
Packet Size
PCS Vendor Specific
Packet Generator
IPG Size
Bit
3.C024h
3.C025h
3.C026h
15:0
Burst Size, RW
Packet Size defined by XGMII columns,
IPG Size defined by XGMII columns,
Default = 16’d256
RW
RW
Default = 16’d5
Default = 16’d1
PCS Vendor Specific
Packet Checker
Control
PCS Vendor Specific
PCS Vendor Specific
Packet Checker
Expected Data LSB
3.C032h
PCS Vendor Specific
Packet Checker
Expected Control
3.C033h
Packet Checker
Expected Data MSB
3.C031h
Bit
3.C030h
TX Packet Checker Enable 1,
RW
0 = Disable, Default
1 = Enable
0
Lane 2 XGMII Data Byte, RW
Default = 8’h00
Lane 0 XGMII Data Byte, RW
Default = 8’h00
Lane 0 XGMII Control
Bit, RW
0 = Data, Default
1 = Control
RX Packet Checker Enable 1,
RW
0 = Disable, Default
1 = Enable
1
Lane 1 XGMII Control
Bit, RW
0 = Data, Default
1 = Control
2
3
Reserved, RO
Lane 2 XGMII Control
Bit, RW
0 = Data, Default
1 = Control
Reserved, RO
Lane 3 XGMII Control
Bit, RW
0 = Data, Default
1 = Control
4
5
Packet Type, RW
00 = Data (fixed)
01 = Data (incremental)
10 = Control (fixed)
11 = Reserved
Reserved, RO
Reserved, RO
Default = 00
6
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
7
15:8
Lane 3 XGMII Data Byte, RW
Default = 8’h00
Lane 1 XGMII Data Byte, RW
Default = 8’h00
1. Both Checkers On == (3.C020h.0=1) OR (3.C020h.1=1) OR (3.C030h.0=1) OR (3.C020h.0=1)
Revision 5.11
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
