Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 15. I/O Specifications—667MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Output (ns)
Hold Time
(T max) (T min)
OV
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
(T min)
IS
(T min)
IH
OH
External Slave Peripheral Interface
PerAddr00:26
PerBE0:1
PerBLast
PerCS0:2
PerData0:15
PerOE
n/a
-
1
-
6.2
0
19.1
27.7
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
8.7
12.8
8.7
8.7
8.7
8.7
8.7
8.7
8.7
8.7
8.7
8.7
8.7
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
na
-
-
n/a
n/a
1.2
n/a
1.7
3.6
n/a
n/a
n/a
n/a
1.2
1
5.7
5.9
6
n/a
0
n/a
1
0
n/a
1
5.8
5.7
n/a
5.7
5.7
n/a
n/a
n/a
0
PerPar0:1
PerReady
PerR/W
n/a
n/a
n/a
0
1
1
PerWE
n/a
n/a
n/a
ExtReset
PerClk
n/a
n/a
n/a
PerClk
PLB clk
PerClk
PerErr
AMCC Proprietary
69
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
