Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 14. I/O Specifications—All Speeds (Sheet 2 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz
and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time
requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
3. These are DDR signals that can change on both the positive and negative clock transitions.
Input (ns)
Output (ns)
Hold Time
(T min)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
(T min)
(T min)
(T
max)
15
IS
IH
OV
OH
EMCTxEn
EMCTxErr
na
na
na
na
2
19.1
19.1
8.7
8.7
EMCTxClk
EMCTxClk
15
2
Internal Peripheral Interface
IIC0SClk
n/a
-
n/a
-
n/a
-
n/a
-
15.3
15.3
15.3
15.3
19.1
-
10.2
10.2
10.2
10.2
8.7
-
IIC0SDA
IIC0SClk
IIC0SClk
IIC1SClk
n/a
-
n/a
-
n/a
-
n/a
-
IIC1SDA
UARTSerClk
UART0_Rx
UART0_Tx
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RI
UART0_RTS
UART1_Rx
UART1_Tx
UART1_DSR/CTS
UART1_DTR/RTS
UART2_Rx
UART2_Tx
Interrupts Interface
IRQ0:15
n/a
-
n/a
-
n/a
n/a
-
n/a
n/a
-
UARTSerClk
UARTSerClk
async
n/a
-
n/a
-
19.1
19.1
19.1
19.1
19.1
-
8.7
8.7
8.7
8.7
8.7
-
n/a
n/a
n/a
n/a
n/a
n/a
-
-
async
-
-
async
n/a
-
n/a
-
async
n/a
n/a
async
n/a
n/a
19.1
19.1
19.1
19.1
19.1
19.1
19.1
8.7
8.7
8.7
8.7
8.7
8.7
8.7
async
n/a
-
n/a
-
UARTSerClk
UARTSerClk
async
n/a
-
n/a
-
n/a
n/a
n/a
-
n/a
-
async
n/a
-
n/a
-
UARTSerClk
UARTSerClk
n/a
n/a
-
-
-
-
n/a
n/a
async
JTAG Interface
TDI
-
-
-
-
na
na
-
na
na
-
na
na
na
na
8.7
na
na
async
async
async
async
async
TMS
TDO
na
-
na
-
19.1
na
TCK
na
na
na
na
TRST
-
-
na
System Interface
Halt
-
-
n/a
-
n/a
-
n/a
19.1
n/a
n/a
8.7
n/a
8.7
n/a
8.7
n/a
n/a
async
async
na
GPIO00:31
SysClk
-
-
-
-
n/a
-
n/a
-
SysErr
n/a
n/a
19.1
n/a
async
async
async
async
na
SysReset
HISRRst
-
-
-
-
-
-
-
-
-
-
-
-
19.1
n/a
TESTEN
n/a
n/a
n/a
n/a
TmrClk
n/a
Trace Interface
TrcClk
n/a
n/a
-
-
-
-
-
-
-
-
19.1
19.1
19.1
19.1
8.7
8.7
8.7
8.7
TRCBS0:2
TrcES0:4
-
-
-
-
-
-
TrcTS0:6
68
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