Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
DDR SDRAM Clock to Write DQS Timing—T
DS
Note 1: All of the DQS signals are referenced to MemClkOut.
Note 2: Clock speed is 333 MHz.
Note 3: The TDS values in the table include 1.5 × 3ns cycle at 333 MHz (3 ns × 1.5 = 4.5 ns).
Note 4: To obtain adjusted values for lower clock frequencies, subtract 4 ns from the values in the following table
and add × 1.5 of the cycle time for the lower clock frequency (T - 4.5 + 1.5 T
).
DS
CYC
Table 18. DDR SDRAM Clock to Write DQS Timing—T
DS
T
(ns)
DS
Signal Name
Minimum
4.76
Maximum
5.07
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
4.78
5.09
4.78
5.10
4.76
5.07
4.79
5.11
4.80
5.13
4.81
5.11
4.79
5.11
4.77
5.07
DDR SDRAM Write Data to DQS Timing—T
T
SD and HD
Note 1: T and T are measured under worst-case conditions.
SD
HD
Note 2: Clock speed for the values in the following table is 333 MHz.
Table 19. DDR SDRAM Write Data to DQS Timing—T and T
SD
HD
THD (ns)
TSD (ns)
Signal Name
Reference Signal
DQS0
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
MemData32:39, DM4
MemData40:47, DM5
MemData48:55, DM6
MemData56:63, DM7
ECC0:7, DM8
0.58
0.62
0.62
0.63
0.68
0.67
0.62
0.65
0.63
0.64
0.55
0.60
0.57
0.54
0.52
0.61
0.55
0.61
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
AMCC Proprietary
73
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
