Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Input/Output Timing
Preliminary Data Sheet
These timing diagrams illustrate the relationship of the timing parameters defined in the I/O Specification tables
that follow.
Figure 5. Input Setup and Hold Waveform
Clock
T
min
IS
T
min
IH
Inputs
Valid
Figure 6. Output Delay and Hold Timing Waveform
Clock
max
T
OV
max
T
OV
max
T
OV
T
min
OH
T
min
OH
T
min
OH
Outputs
High (Drive)
Float (High-Z)
Valid
Valid
Low (Drive)
66
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