Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
DDR SDRAM Write Operation
Preliminary Data Sheet
The following timing chart shows the relationship between the signals involved in a DDR write operation.
Figure 8. DDR SDRAM Write Cycle Timing
PLB Clk
MemClkOut
T
DS
T
T
HA
SA
Addr/Cmd
DQS
T
SD
T
SD
MemData
T
HD
T
HD
T
T
T
T
T
= Setup time for address and command signals to MemClkOut
SA
HA
SD
HD
DS
= Hold time for address and command signals from MemClkOut
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
DDR SDRAM Read and Write I/O Timing—T and T
SA
HA
Note 1: Clock speed is 333 MHz. T and T are referenced to MemClkOut.
SA
HA
Note 2: Memory clock signal is shifted by 90° from the internal clock.
Table 17. DDR SDRAM Read and Write I/O Timing—T and T
SA
HA
T
(ns)
T
(ns)
HA
SA
Signal Name
Minimum
1.32
Minimum
1.2
MemAddr00:12
BA0:1
1.15
1.49
BankSel0:3
ClkEn0:3
CAS
1.12
1.52
1.29
1.45
1.24
1.14
RAS
1.29
1.48
WE
1.35
1.43
72
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
