Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 6 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
UART Peripheral Interface
Serial clock input that provides an alternative to the
internally generated serial clock. Used in cases where
the allowable internally generated clock rates are not
satisfactory.
UARTSerClk
I
3.3V LVTTL
1, 4
UART0_Rx
UART0 Receive data.
I
O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1, 4
UART0_Tx
UART0 Transmit data.
4
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RTS
UART0 Data Carrier Detect.
UART0 Data Set Ready.
UART0 Clear To Send.
UART0 Data Terminal Ready.
UART0 Request To Send.
6
I
6
I
1, 4, 6
O
O
4
4
3.3V LVTTL
w/pull-up
UART0_RI
UART0 Ring Indicator.
I
1, 4
UART1_Rx
UART1_Tx
UART1 Receive data.
UART1 Transmit data.
I
3.3V LVTTL
3.3V LVTTL
1, 4
1, 4
O
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
UART1_DSR/CTS
UART1_DTR/RTS
I
3.3V LVTTL
3.3V LVTTL
1, 4
1, 4
UART1 Request To Send or Data Terminal Ready. The
choice is determined by a DCR register bit setting.
O
UART2_Rx
UART2 Receive data.
UART2 Transmit data.
I
3.3V LVTTL
3.3V LVTTL
1, 4
1, 4
UART2_Tx
O
Interrupts Interface
External interrupt Requests 0 through 15.
These pins are multiplexed with GPIO16:31
IRQ0:15
I
3.3V LVTTL
1, 5
1, 4
System Interface
Halt
Halt from external debugger.
I
3.3V LVTTL
3.3V LVTTL
General purpose I/O 0 through 31.
GPIO00:31
I/O
The GPIOs are multiplexed with IRQs, and Trace signal
IO. Setting is done with the DCR register bits.
SysClk
Main system clock input.
Set to 1 when a machine check is generated.
Not used.
I
O
I
3.3V LVTTL
3.3V LVTTL
NA
SysErr
SysPartSel
3
Main system reset. External logic can drive this pin low
(minimum of 16 cycles) to initiate a system reset. A reset
of the PPC440SPe can also be initiated by software.
SysReset
ExtReset
I
3.3V LVTTL
3.3V LVTTL
1, 2
External Reset. During the PPC440SPe’s reset phase
this signal is at down level.
O
AMCC Proprietary
55
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
