Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 4 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
MemDCFdbkD
Description
I/O
Type
Notes
2.5(1.8)V
DDR SDRAM
Feedback driver, for I/O timing measurements.
O
Feedback receiver. Connect externally to
MemDCFdbkD.
2.5(1.8)V
DDR SDRAM
MemDCFdbkR
MemODT0:3
I
2.5(1.8)V
DDR SDRAM
Memory on-die termination control
O
2.5(1.8)V
DDR SDRAM
Volt Ref Rcv
Memory reference voltage (SV
) input.
MemVRef0
MemVRef1
I
I
REF
2.5(1.8)V
DDR SDRAM
Volt Ref Sup
Memory reference voltage (SV
) supplemental input.
REF
2.5(1.8)V
DDR SDRAM
RAS
WE
Row Address Strobe.
Write Enable.
O
O
2.5(1.8)V
DDR SDRAM
Ethernet Interface
EMCCD
Collision detection.
Carrier sense.
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
EMCCrS
EMCMDClk
Management data clock.
O
Transfer command and status information between MII
and PHY.
EMCMDIO
I/O
3.3V LVTTL
EMCRxD0:7
EMCRxDV
EMCRxErr
EMCRxClk
EMCRefClk
EMCTxClk
EMCGTxClk
EMCTxD0:7
EMCTxEn
Receive data.
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Receive data valid.
Receive error.
I
Receive clock.
I
Reference clock.Typical use: GMII Gigabit interface
Transmit clock for 10/100 Mb/s.
Ethernet gigabit transmit clock. 125MHz to PHY
Transmit data.
I
I
O
O
O
O
Transmit data enabled.
Transmit error.
EMCTxErr
AMCC Proprietary
53
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
