Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
Input PCI & PCI-X Clock.
I/O
Type
Notes
Note:If the PCI-X interface is not being used, drive this
pin with a 3.3V clock signal at a frequency
between 1 and 66MHz
PCIX0Clk
I
3.3V PCI
Indicates the driving device has decoded its address as
the target of the current access.
PCIX0DevSel
PCIX0ECC5:2
PCIX0Frame
I/O
I/O
I/O
3.3V PCI
4
ECC check bits 5–2. All ECC bits are valid only for PCIX
DDR mode 2.
3.3V PCI or
Note:See PCIXPar for ECC0.
See PCIXAck64 for ECC1.
See PCIXReq64 for ECC6.
See PCIXPar64 for ECC7.
1.5V PCI for
mode 2
Driven by the current master to indicate beginning and
duration of an access.
3.3V PCI
3.3V PCI
4
4
Indicates that the specified agent is granted access to
the PCI-X bus. When Arbitration is internal to the
PPC440SPe, all GRANTS Gnt0:3 are outputs. When
arbitration is external, only Gnt 0 is used as an Input.
PCIX0Gnt0
I/O
O
PCIX0Gnt1:3
Used as a chip select during configuration read and
write transactions. If the PCI-X is a Host, during
Configuration the ISDSEL is an Output that duplicates
the AD17. The ISDSEL is always 3.3V even in Mode 2
DDR
PCIX0IDSel
I/O
3.3V PCI
5
4
PCIX0INTA
PCIX0IRDY
Level sensitive PCI interrupt.
O
3.3V PCI
3.3V PCI
Indicates initiating agent’s ability to complete the current
data phase of the transaction.
I/O
3.3V PCI or
PCIX0M66En
Capable of 66MHz operation.
I
1.5V PCI for
mode 2
Even parity indicator or ECC0.
3.3V PCI or
Normally used to indicate even parity across
PCIAD31:00 and BE3:0.
PCIX0Par/PCIX0ECC0
I/O
1.5V PCI for
mode 2
Used as ECC0 for PCIX0 mode 2.
Even parity indicator or ECC7.
Normally used to indicate even parity across
PCIXAD63:32 and BE7:4 for PCIX0
3.3V PCI or
PCIX0Par64/PCIX0ECC7
PCIX0PErr
I/O
I/O
1.5V PCI for
mode 2
or
Used as ECC7 for PCIX0 mode 2.
Reports data parity errors during all PCI transactions
except a Special Cycle.
3.3V PCI
3.3V PCI
4
4
An indication to the PCI-X arbiter that the specified
agent wishes to use the bus.
PCIX0Req0
I/O
I
When Arbitration is internal to the PPC440SPe, all
REQS Req0:3 are Inputs. When arbitration is external,
only Req 0 is used as an output.
PCIX0Req1:3
AMCC Proprietary
51
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
