Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 3 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
Request 64-bit transfer or ECC6.
3.3V PCI or
Normally used by the current bus master to indicate a
64-bit transfer.
PCIX0Req64/PCIX0ECC6
I/O
4
1.5V PCI for
mode 2
Used as ECC6 for PCIX0 mode 2.
PCIX0Reset
PCIX0SErr
Sets PCI device registers and logic to a consistent state.
O
3.3V PCI
3.3V PCI
Reports address parity errors, data parity errors on the
Special Cycle command, or other catastrophic system
errors.
I/O
4
Indicates the current target is requesting the master to
stop the current transaction.
PCIX0Stop
I/O
I/O
3.3V PCI
3.3V PCI
4
4
Indicates the target agent’s ability to complete the
current data phase of the transaction.
PCIX0TRDY
Voltage control output. Used to control the voltage
regulator supplying the PCI I/O voltage. See PCIX0Cap
signal.
PCIX0VC
O
I
3.3(1.5)V PCI
VPCIXDDR
0 = 3.3V (PCI I/O)
1 =1.5V (PCI-X DDR)
Voltage reference input for PCI-X mode 2/DDR (1.5V)
I/O. Not used for PCI or PCI-X mode 1.
PCIX0VRef0:1
DDR SDRAM Interface
BA0:2
5
2.5(1.8)V
DDR SDRAM
Bank Address supporting up to 8 internal banks.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
O
O
O
O
O
2.5(1.8)V
DDR SDRAM
BankSel0:3
CAS
2.5(1.8)V
DDR SDRAM
2.5(1.8)V
DDR SDRAM
ClkEn0:3
DM0:8
Clock Enable. One for each external bank.
Memory write data byte lane masks. MEMDM8 is the
byte lane mask for the ECC byte lane.
2.5(1.8)V
DDR SDRAM
2.5(1.8)V
DDR SDRAM
DIFF
DQS0:8
DQS0:8
Byte lane data strobe. DQS8 is the data strobe for the
ECC byte lane. These signals are differential pairs.
I/O
2.5(1.8)V
DDR SDRAM
ECC0:7
ECC check bits 0:7.
I/O
O
Memory address bus.
2.5(1.8)V
DDR SDRAM
MemAddr14:00
Note:MemAddr14 is the most significant bit (msb).
Subsystem clocks. The Clock signal (differential pair) is
duplicated six times to support high loading:
2.5(1.8)V
DDR SDRAM
DIFF
MemClkOut0:5
MemClkOut0:5
Six clocks can be used for two unbuffered DIMMS.
O
Each individual clock signal can be enabled by
programming the SDR0_DDRCLKSET register.
Memory data bus.
2.5(1.8)V
DDR SDRAM
MemData63:00
52
I/O
Note:MemData63 is the most significant bit (msb).
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
