Revision 1.23 - Sept 21, 2006
PowerPC 440SPe Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 5 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
External Slave Peripheral Interface - EBC
Peripheral address bus.
PerAddr00:26
O
3.3V LVTTL
1
1
Note:PerAddr00 is the most significant bit (msb).
PerBE0:1
PerBLast
PerCS0:2
External peripheral data bus byte enable.
O
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Used by the peripheral controller to indicates the last
transfer of a memory access.
External peripheral device select.
Peripheral data bus.
PerData00:15
PerOE
I/O
O
3.3V LVTTL
3.3V LVTTL
1
Note:PerData0 is the most significant bit (msb).
Used by peripheral controller or DMA controller
depending upon the type of transfer involved. When the
PPC440SPe is the bus master, it enables the selected
device to drive the bus.
PerPar0:1
PerReady
External peripheral data bus byte parity.
I/O
I
3.3V LVTTL
3.3V LVTTL
1
1
Used by a peripheral slave to indicate it is ready to
transfer data.
The peripheral controller set this signal to High for a
Read from external memory, and to Low for a Write.
PerR/W
O
3.3V LVTTL
PerWE
PerClk
Write Enable.
O
O
3.3V LVTTL
3.3V LVTTL
Peripheral clock used by synchronous peripheral slaves.
External error used as an input to record external slave
peripheral errors.
PerErr
I
3.3V LVTTL
1, 5
IIC Peripheral Interface
IIC0SClk
IIC0 Serial Clock.
IIC0 Serial Data.
IIC1 Serial Clock.
IIC1 Serial Data.
I/O
I/O
I/O
I/O
3.3V IIC
3.3V IIC
3.3V IIC
3.3V IIC
1, 2
1, 2
1, 2
1, 2
IIC0SDA
IIC1SClk
IIC1SDA
54
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
