Revision 1.26 – October 15, 2007
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
Features include:
• USB 2.0 Host with internal PHY
– Fully compliant to the following specifications:
• Universal Serial Bus Specification, Revision 2.0.
• Enhanced Host Controller Interface (EHCI) Specification for USB, Revision 1.0.
• Open Host Controller Interface (OHCI) Specification for USB, Revision 1.0a.
– One USB port provided through a UTMI transceiver interface connected to the internal USB 2.0 Physical
Layer (Single port USB 2.0 Physical Layer UTMI+ version 1.05).
– One USB EHCI high speed (480Mbps) host controller with 1024-byte packet buffer.
– One USB OHCI full/low speed (12Mbps/1.5Mbps) host controller.
– Host controller does not support high-bandwidth isochronous transfers
– Independent OPB master and slave ports which run asynchronously to the USB clocks.
– USB OHCI/EHCI registers and data structures implemented in Big Endian format.
• USB 2.0 Device UTMI or USB 2.0 Device with internal PHY (excluding USB 2.0 Host function)
– Device support provides six end points (3 IN, 3 OUT)
– 8192-byte FIFO by endpoint (supports high-bandwidth isochronous transfers, double buffering of 1024-
byte packets)
– FIFOs are not shared between IN and OUT endpoints
– Two USB 2.0 device end points have DMA dedicated channels (DMA-to-PLB4)
NAND Flash Controller
The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND
Flash devices. It provides both direct command, address, and data access to the external device as well as a
memory-mapped linear region that generates data accesses. NAND Flash data is transferred on the peripheral
data bus.
Features include:
• One to four banks supported on EBC
• Direct interface to:
– Discrete NAND Flash devices (up to four devices)
– SmartMedia Card socket (22-pins)
• Device Sizes:
– 4MB and larger supported for read/write access
– 4MB to 256MB for boot-from-NAND flash (size supported depends on addressing mode)
• (512 + 16)-B or (2K + 64)-B page sizes supported
• Boot-from-NAND
– Execute up to 4KB of boot code out of first block
– Automatic page read accesses performed based on device configuration and addressing mode
• ECC provides single-bit error correction and double-bit error detection in each 256B of stored data
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor.
Features include:
• 32-bit Time Base Counter driven by the OPB bus clock
• Seven 32-bit compare timers
AMCC Proprietary
17
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
