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PPC440EPX-SPAFFFTS 参数 Datasheet PDF下载

PPC440EPX-SPAFFFTS图片预览
型号: PPC440EPX-SPAFFFTS
PDF下载: 下载PDF文件 查看货源
内容描述: 440EPx的PowerPC嵌入式处理器 [PowerPC 440EPx Embedded Processor]
分类和应用: PC
文件页数/大小: 94 页 / 3193 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.26 – October 15, 2007  
440EPx – PPC440EPx Embedded Processor  
General Purpose IO (GPIO) Controller  
Preliminary Data Sheet  
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master  
accesses.  
• 64 GPIOs are multiplexed with other functions. DCRs control whether a particular pin that has GPIO  
capabilities acts as a GPIO or is used for another purpose.  
• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,  
tri-stated if output bit is 1).  
Universal Interrupt Controller (UIC)  
Two Universal Interrupt Controllers (UIC) are employed. They provide control, status, and communications  
necessary between the external and internal sources of interrupts and the on-chip PowerPC processor.  
Note: Processor specific interrupts (for example, page faults) do not use UIC resources.  
Features include:  
• 10 external interrupts  
• Edge triggered or level-sensitive  
• Positive or negative active  
• Non-critical or critical interrupt to the on-chip processor  
• Programmable interrupt priority ordering  
• Programmable critical interrupt vector for faster vector processing  
JTAG  
Features include:  
• IEEE 1149.1 Test Access Port  
• JTAG Boundary Scan Description Language (BSDL)  
• Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use  
with this port.  
18  
AMCC Proprietary  
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