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PPC440EPX-SPAFFFTS 参数 Datasheet PDF下载

PPC440EPX-SPAFFFTS图片预览
型号: PPC440EPX-SPAFFFTS
PDF下载: 下载PDF文件 查看货源
内容描述: 440EPx的PowerPC嵌入式处理器 [PowerPC 440EPx Embedded Processor]
分类和应用: PC
文件页数/大小: 94 页 / 3193 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.26 – October 15, 2007  
440EPx – PPC440EPx Embedded Processor  
Preliminary Data Sheet  
• Secure Socket Layer (SSL) and Transport Layer Security (TLS) features  
– Packet transforms  
– One-pass hash-then-encrypt for SSL and TLS packet transforms for inbound packet using Stream Cipher  
• Secure Real-Time Protocol (sRTP) features  
– Packet transforms  
– ROC removal and TAG insertion  
– Variable bypass offset of header length per packet  
• IPsec/SSL security acceleration engine  
• DES, 3DES, AES, ARC-4 encryption  
• MD-5, SHA-1 hashing, HMAC encrypt-hash and hash-decrypt, and KASUMI  
• Public key acceleration for RSA, DSA and Diffie-Hellman  
• True or pseudo random number generators  
– Non-deterministic true random numbers  
– Pseudo random numbers with lengths of 8B or 16B  
– ANSI X9.17 Annex C compliant using a DES algorithm  
• Interrupt controller  
– Fifteen programmable, maskable interrupts  
– Initiate commands via an input interrupt  
– Sixteen programmable interrupts indicating completion of certain operations  
– All interrupts mapped to one level- or edge-sensitive programmable interrupt output  
• DMA controller  
– Autonomous, 4-channel  
– 1024-words (32 bits/word) per DMA transfer  
– Scatter/gather capability with byte aligned addressing  
KASUMI Algorithm (optional)  
• Key scheduling hardware  
f8 and f9 algorithm support  
• Automatic data padding mechanism for f9 algorithm  
• KASUMI encryption and decryption modes  
• 32-bit slave interface  
• Fully synchronous to PLB clock  
PCI Controller  
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is  
designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices.  
Reference Specifications:  
• PowerPC CoreConnect Bus (PLB) Specification Version 3.1  
• PCI Specification Version 2.2  
• PCI Bus Power Management Interface Specification Version 1.1  
Features include:  
• PCI 2.2  
• Frequency to 66MHz  
• 32-bit bus  
• PCI Host Bus Bridge or an Adapter Device's PCI interface  
• Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an  
external arbiter  
• Support for Message Signaled Interrupts  
• Simple message passing capability  
• Asynchronous to the PLB  
AMCC Proprietary  
13  
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