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PPC440EPX-SPAFFFTS 参数 Datasheet PDF下载

PPC440EPX-SPAFFFTS图片预览
型号: PPC440EPX-SPAFFFTS
PDF下载: 下载PDF文件 查看货源
内容描述: 440EPx的PowerPC嵌入式处理器 [PowerPC 440EPx Embedded Processor]
分类和应用: PC
文件页数/大小: 94 页 / 3193 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.26 – October 15, 2007  
440EPx – PPC440EPx Embedded Processor  
Serial Ports (UART)  
Preliminary Data Sheet  
Features include:  
• Up to four ports in the following combinations:  
– One 8-pin (UART0)  
– Two 4-pin (UART0 and UART1)  
– One 4-pin (UART0) and two 2-pin (UART1 and UART2)  
– Four 2-pin (UART0, UART1, UART2, and UART3)  
• Selectable internal or external serial clock to allow wide range of baud rates  
• Register compatibility with NS16750 register set  
• Complete status reporting capability  
• Fully programmable serial-interface characteristics  
• Supports DMA using internal DMA function on PLB3  
IIC Bus Controller  
Features include:  
• Two IIC interfaces provided  
2
• Support for Philips® Semiconductors I C Specification, dated 1995  
• Operation at 100kHz or 400kHz  
• 8-bit data  
• 10- or 7-bit address  
• Slave transmitter and receiver  
• Master transmitter and receiver  
• Multiple bus masters  
• Two independent 4 x 1 byte data buffers  
• Twelve memory-mapped, fully programmable configuration registers  
• One programmable interrupt request signal  
• Provides full management of all IIC bus protocols  
• Programmable error recovery  
• Includes an integrated bootstrap controller (BSC) that is multiplexed with the second IIC interface  
Serial Peripheral Controller (SPI/SCP)  
The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous,  
character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on  
the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.  
Features include:  
• Three-wire serial port interface  
• Full-duplex synchronous operation  
• SCP bus master  
• OPB bus slave  
• Programmable clock rate divider  
• Clock inversion  
• Reverse data  
• Local data loop back for test  
Universal Serial Bus 2.0 (USB)  
The USB 2.0 interface provides both device and host support. One interface provides host or device support and  
operates through an internal PHY. The other interface provides device support only through the UTMI interface  
with no internal PHY.  
16  
AMCC Proprietary  
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