Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Table 9. Recommended DC Operating Conditions (Sheet 2 of 3)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
V
Notes
SVREF+0.18
SVDD+0.3
Input Logic High (2.5V DDR SDRAM)
Input Logic High (1.8V DDR2 SDRAM)
2
SVREF+0.125
1.7
SVDD+0.3
V
Input Logic High (2.5V CMOS, 3.3V tolerant
receiver)
V
VIH
0.5OVDD
VREF+0.10
+2.0
OVDD+0.5
VI/O+0.50
Input Logic High (3.3V PCI-X)
V
V
V
V
V
1
1
Input Logic High (1.5V PCI-X DDR)
Input Logic High (3.3V LVTTL)
+3.6
SVREF-0.18
Input Logic Low (2.5V DDR SDRAM)
Input Logic Low (1.8V DDR2 SDRAM)
-0.3
SVREF-0.125
0.7
-0.3
Input Logic Low (2.5V CMOS, 3.3V tolerant
receiver)
V
VIL
0.35OVDD
Input Logic Low (3.3V PCI-X)
-0.5
-0.5
V
V
V
V
V
1
1
VREF-0.10V
Input Logic Low (1.5V PCI-X DDR)
Input Logic Low (3.3V LVTTL)
0
+0.8
SVDD
Output Logic High (2.5V DDR SDRAM)
Output Logic High (1.8V DDR2 SDRAM)
+1.95
SVDD-0.45
SVDD
Output Logic High (2.5V CMOS, 3.3V tolerant
receiver)
2.0
V
VOH
0.9OVDD
OVDD
OVDD
Output Logic High (3.3V PCI-X)
V
V
V
V
V
1
1
Output Logic High (1.5V PCI-X DDR)
Output Logic High (3.3V LVTTL)
+2.4
0
Output Logic Low (2.5V DDR SDRAM)
Output Logic Low (1.8V DDR2 SDRAM)
0.45
0.45
0
Output Logic Low (2.5V CMOS, 3.3V tolerant
receiver)
0.4
V
VOL
0.1OVDD
Output Logic Low (3.3V PCI-X)
Output Logic Low (1.5V PCI-X DDR)
Output Logic Low (3.3V LVTTL)
V
V
V
1
1
0
0
+0.4
1
Input Leakage Current (with no internal pull-up
or pull-down)
IIL1
IIL2
IIL3
μA
Input Leakage Current (with internal pull-down)
Input Leakage Current (with internal pull-up)
0 (LPDL)
200 (MPUL)
0 (MPUL)
μΑ
5
5
-150 (LPDL)
μA
AMCC Proprietary
65
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
