Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
+1.7
Typical
+1.8
Maximum
+1.9
Unit
V
Notes
VDD
Logic Supply Voltage
I/O Supply Voltage
4
4
4
3
3
2
1
OVDD
SVDD
+3.0
+3.3
+3.6
V
DDR SDRAM Supply Voltage (DDR clock up to 166MHz)
PLL Supply Voltages
+2.3
+2.5
+2.7
V
AxVDD
SVREF
+1.65
+1.15
SVREF+0.18
0.5OVDD
+2.0
+1.8
+1.95
V
DDR SDRAM Reference Voltage
+1.25
+1.35
V
SVDD+0.3
OVDD+0.5
Input Logic High (2.5V SSTL)
V
Input Logic High (3.3V PCI-X)
V
VIH
Input Logic High (3.3V LVTTL, 5V tolerant receiver)
Input Logic Low (2.5V SSTL)
+5.5
V
SVREF-0.18
-0.3
V
0.35OVDD
Input Logic Low (3.3V PCI-X)
-0.5
V
1
1
1
VIL
Input Logic Low (3.3V LVTTL, 5V tolerant receiver)
Output Logic High (2.5V SSTL)
0
+0.8
V
SVDD
+1.95
0.9OVDD
V
OVDD
OVDD
Output Logic High (3.3V PCI-X)
V
VOH
Output Logic High (3.3V LVTTL, 5V tolerant receiver)
Output Logic Low (2.5V SSTL)
+2.4
0
V
0.55
V
0.1OVDD
Output Logic Low (3.3V PCI-X)
V
VOL
Output Logic Low (3.3V LVTTL, 5V tolerant receiver)
Input Leakage Current (No pull-up or pull-down)
0
0
+0.4
0
V
IIL1
IIL2
IIL3
μA
Input Leakage Current for Pull-Down
Input Leakage Current for Pull-Up
0 (LPDL)
-150 (LPDL)
200 (MPUL)
0 (MPUL)
5
5
μA
μA
Input Max Allowable Overshoot (3.3V LVTTL, 5V tolerant
receiver)
VIMAO
+5.5
V
V
V
V
Input Max Allowable Undershoot (3.3V LVTTL, 5V tolerant
receiver)
VIMAU
-0.6
-0.6
Output Max Allowable Overshoot (3.3V LVTTL, 5V tolerant
receiver)
VOMAO
+5.5
Output Max Allowable Undershoot (3.3V LVTTL,
5V tolerant receiver)
VOMAU3
58
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
