Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Peripheral Interface Clock Timings
Parameter
PCIXClk input frequency (asynchronous mode)
PCIXClk period (asynchronous mode)
PCIXClk input high time
Min
Max
Units
MHz
ns
Notes
–
133.33
2
7.5
–
40% of nominal period
60% of nominal period
ns
PCIXClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
MHz
ns
400
–
EMCMDClk output high time
EMCMDClk output low time
EMCTxClk input frequency MII(RMII)
EMCTxClk period MII(RMII)
EMCTxClk input high time
160
–
ns
160
–
ns
2.5(5)
25(50)
MHz
ns
40(20)
35% of nominal period
35% of nominal period
2.5(5)
400(200)
–
ns
EMCTxClk input low time
–
ns
EMCRxClk input frequency MII(RMII)
EMCRxClk period MII(RMII)
EMCRxClk input high time
EMCRxClk input low time
25(50)
MHz
ns
40(20)
400(200)
35% of nominal period
35% of nominal period
–
–
–
ns
ns
EMCRefClk input frequency
EMCRefClk period
50
MHz
ns
20
EMCRefClk input high time
EMCRefClk input low time
PerClk output frequency (for ext. master or sync. slaves)
PerClk period
45% of nominal period
45% of nominal period
–
55% of nominal period
55% of nominal period
66.66
ns
ns
MHz
ns
15
–
PerClk output high time
50% of nominal period
33% of nominal period
66% of nominal period
50% of nominal period
ns
PerClk output low time
ns
1000/(2TOPB1+2ns)
UARTSerClk input frequency
UARTSerClk period
–
MHz
ns
1
1
1
1
2TOPB+2
TOPB+1
–
–
–
UARTSerClk input high time
UARTSerClk input low time
ns
T
OPB+1
ns
62
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
