Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
DDR SDRAM Read Operation
The read data capture logic is responsible for capturing the data outputs from the SDRAM devices and passing the
data back to the system clock domain. The data strobe signal (DQS) signals used to capture data are delayed to
ensure that the rising and falling edges of these strobes are in the middle of the valid window of data.
DDR devices send a DQS coincident with the read data so that the data can be reliably captured by the
PPC440EPx. The edges of these strobe signals are aligned with the data output by the SDRAM devices.
In order to reliably latch the data into a synchronizing FIFO, the PPC440EPx produces an internal, delayed version
of DQS. The amount of delay is user programmable. In the example shown in Figure , the delay is set to
approximately 25% of the system clock. A delay compensation circuit in the PPC440EPx keeps this delay
constant.
Figure 11. DDR SDRAM DQS Read Timing
MemClkOut
DQS
DQS delay
MemData
Delayed DQS
(data strobe)
DQS Delay programmed in bitfields DDR0_17[DDQSD0], DDR0_18[DDQD4:1] and DDR0_19[DDQD8:5].
T
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
SD
HD
T
90
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