Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Boot Configuration
Data Sheet
The PPC440EPx supports several configurable boot parameters that must be initialized prior to booting. These
parameters are configured by one of several default boot options or programmed by data read from an IIC serial
EEPROM (see “Serial EEPROM” below). Strap signals sampled during reset select which method is used to
initialize the boot parameters (see “Strapping” below).
Strapping
The Bootstrap Controller selects the boot options based on the state of the strap signals during reset. The strap
signals are sampled on the rising edge of SysClk while SysReset is driven low. They must not change state until
after SysReset is driven high in order to guarantee the correct boot option is selected.
These pins are used for strap functions only during reset. Following reset, they are used as UART signals. The
UART signal names are shown in parentheses following the pin number.
Note: To isolate the strapping pins, the ExtReset signal may be used as a buffer enable or multiplexer select.
The following table lists the strapping pins along with their functions and boot strap options:
Table 29. Strapping Pin Assignments
Pin Strapping
Function
Option
C28
C29
A29
(UART0_DCD)
(UART0_DSR)
(UART0_CTS)
A1
Serial device is disabled. Each of the six options (A–F) is a
combination of boot source, boot-source width, and clock
frequency specifications. Refer to the IIC Bootstrap Controller
chapter in the PPC440EPx Embedded Processor User’s
Manual for details.
0
0
0
0
0
0
1
1
0
1
0
1
B1
C
D1
E1
F
1
1
1
0
1
0
0
0
1
Serial device is enabled. Boot Option G and H enable the
Bootstrap Controller to program boot parameters using data
read from an IIC serial EEPROM.
G (0xA8)
Option G and H support different IIC addresses.
H (0xA4)
1
1
1
Option G - Address 0xA8 is left justified (0x1010100 + R/W bit).
Option H - Address 0xA4 is left justified (0x1010010 + R/W bit).
1. Bootstrap options A, B, D, and E result in a PLL Forward Divisor B setting such that Forward Divisor B output frequency exceeds the CPU
clock frequency. Following a power up, system reset or chip reset (when CPR0_ICFG[RLI] = 0), FWDVB and PRBDV0 must be re-
programmed as documented in the PowerPC 440EPx/GRx Embedded Processor User’s Manual in the Bootstrap Options section. The
dividers must be re-programmed before the DDR is tuned such that the output of PLL Forward Divider B does not exceed the CPU clock
frequency.
Serial EEPROM
Boot Options G and H enable the Bootstrap Controller to read 16 bytes of configuration data from a serial
EEPROM attached to the IIC0 bus after SysReset de-asserts. The Bootstrap Controller stores the data in the
SDR0_SDSTP0:3 registers.
Note: The IIC serial EEPROM must have a one-byte base address. Multi-byte base addresses are not supported.
The initialization settings and their default values are covered in detail in the PowerPC 440EPx/GRx Embedded
Processor User’s Manual.
92
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