Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Date
Version
Contents of Modification
Indicate that two USB analog voltages are needed with separate filters.
Correct descriptions of LeakTest, RcvrInh, ModeCtrl, RefEn, and DrvrInh1:2 signals.
Add information concerning address bus loading on DDR SDRAMs.
Additions to information on USB crystal/oscillator inputs.
Restore leaded PNs.
12/28/2006
1.18
01/10/2007
02/01/2007
1.19
1.20
Update DDR2/1 SDRAM timing and board design data.
Update power data.
Change VIL.
Change Typical Power on first page.
Change VIL back to what it was.
03/12/2007
1.21
Update package drawing with another view.
Remove all valid USB oscillator and crystal frequencies except 48MHz.
Added more information to the Thermal Monitor section.
Changes to Figure 3.
04/23/2007
07/18/2007
08/06/2007
1.22
1.23
1.24
Added Assembly Recommendations, added Tables 3 and 4.
Added recommendations for Unused I/O.
Updated signal description in table 7 for signals SPCClkOUT, SCPDI, SCPDO, LeakTest and
LeakTest2.
Updated Table 19 to include reference clocks.
Removed all references to TBI and RTBI as these modes are not supported due to errata:
Chip_4 and Chip_5.
Added voltage reference to Figures 4, 5, and 6
08/24/2007
1.25
Corrected I/O comments for UART and Ethernet signals in Table 6.
Removed Note 2 from Table 7 and added section on Analog Voltage Filter
Added Figure and Table for Overshoot and Undershoot.
Added section on Power Sequencing.
Added slew rate and jitter requirements for GMCRefClk in Table 20.
Added note in Strapping section
Changed GPIO26[IIC0SData] to [GPIO26]IIC0SData.
Added figures showing setup, hold, output valid and output hold timing for RGMII signals.
Corrected telephone numbers on the last page.
10/15/2007
01/072008
1.26
1.27
Corrected RGMII timing relative to GMCnTXClk in table 21.
Pull up recommendations to Table 9 for PCI signals.
Correction to table 19 “GMCRefClk Period” unit column, changed MHz to ns.
Corrected DC Overshoot in Overshoot.
Added note for SMIISync signal to I/O Specification table.
Added timing references to I/O Specification tables.
Added an unused termination recommendation for Ethernet interfaces.
Added TrcClk supported range to Clock Specification table.
Remove tape and reel as a shipping option.
Corrected GMCTxClk entry in Table 8 to indicate that it is an input.
Replaced 16750 compatible UART to 16550
Replaced NS16750 with NS16550.
Updated the Drvrinh1:2.
03/18/2008
07/22/2008
1.28
1.29
Updated the Analog Voltage Filter from SAVDD to EAVDD and SAGND to EAGND
Updated the RejectPkt0:1 note in table 8.
Update to table 6 signals list: F02, AB33, and AL27
Add JTAG timing specification to Table 20.
94
AppliedMicro Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
