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PPC405CR-3BC200CZ 参数 Datasheet PDF下载

PPC405CR-3BC200CZ图片预览
型号: PPC405CR-3BC200CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 405CR的PowerPC嵌入式处理器 [PowerPC 405CR Embedded Processor]
分类和应用: PC
文件页数/大小: 42 页 / 820 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.02 – January 11, 2005  
PPC405CR – PowerPC 405CR Embedded Processor  
Data Sheet  
Table 6. Signal Functional Description (Sheet 2 of 5)  
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.  
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull-up or pull-down required.  
7. Pull-up may be required. See “External Bus Control Signals” on page 22.  
Signal Name  
Description  
Peripheral chip select bank 0.  
I/O  
Type  
Notes  
5V tolerant  
3.3V LVTTL  
PerCS0  
O
7
Seven additional peripheral chip selects  
or  
5V tolerant  
3.3V LVTTL  
PerCS1:7[GPIO10:16]  
PerOE  
O[I/O]  
O
1, 7  
7
General Purpose I/O. To access this function, software must toggle a  
DCR register bit.  
Used by either peripheral controller or DMA controller depending  
upon the type of transfer involved. When the PPC405CR is the bus  
master, it enables the selected device to drive the bus.  
5V tolerant  
3.3V LVTTL  
Used by the PPC405CR when not in external master mode, as output  
by either the peripheral controller or DMA controller depending upon  
the type of transfer involved. High indicates a read from memory, low  
indicates a write to memory.  
5V tolerant  
3.3V LVTTL  
PerR/W  
I/O  
1
Otherwise it used by the external master as an input to indicate the  
direction of transfer.  
5V tolerant  
3.3V LVTTL  
PerReady  
PerBLast  
Used by a peripheral slave to indicate it is ready to transfer data.  
I
1
Used by the PPC405CR when not in external master mode,  
otherwise used by external master. Indicates the last transfer of a  
memory access.  
5V tolerant  
3.3V LVTTL  
I/O  
1, 7  
DMAReq0:3 are used by slave peripherals to indicate they are  
prepared to transfer data.  
5V tolerant  
3.3V LVTTL  
DMAReq0:3  
DMAAck0:3  
I
1
6
1
DMAAck0:3 are used by the PPC405CR to indicate that data  
transfers have occurred.  
5V tolerant  
3.3V LVTTL  
O
5V tolerant  
3.3V LVTTL  
EOT0:3/TC0:3  
End Of Transfer/Terminal Count.  
I/O  
24  
AMCC  
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