Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
If your system-level test methodology permits, input-only signals can be connected together and terminated
through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that
the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the
PPC405CR.
Unused I/Os
Strapping of some pins may be necessary when they are unused. Although the PPC405CR requires only the pull-
up and pull-down terminations as specified in the “Signal Functional Description” on page 23, good design practice
is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral and
SDRAM buses should be configured and terminated as follows:
•
Peripheral interface—PerAddr0:31, PerData0:31, and all of the control signals are driven by default. Termi-
nate PerReady high and PerError low.
•
SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405CR
to actively drive all of the SDRAM address, data, and control signals.
External Bus Control Signals
All peripheral bus control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck)
are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerPC 405CR Embedded
Processor User’s Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these
control signals between transactions and/or when an external master owns the peripheral bus. As a result, a pull-
up resistor should be added to those control signals where an undriven state may affect any devices receiving that
particular signal.
The following table lists all of the I/O signals provided by the PPC405CR. Please refer to “Signals Listed Alphabet-
ically” on page 11 for the pin number to which each signal is assigned.
22
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
