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PPC405CR-3BC200CZ 参数 Datasheet PDF下载

PPC405CR-3BC200CZ图片预览
型号: PPC405CR-3BC200CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 405CR的PowerPC嵌入式处理器 [PowerPC 405CR Embedded Processor]
分类和应用: PC
文件页数/大小: 42 页 / 820 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.02 – January 11, 2005  
PPC405CR – PowerPC 405CR Embedded Processor  
Data Sheet  
Table 6. Signal Functional Description (Sheet 5 of 5)  
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.  
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull-up or pull-down required.  
7. Pull-up may be required. See “External Bus Control Signals” on page 22.  
Signal Name  
Description  
I/O  
Type  
Notes  
General Purpose I/O  
or  
GPIO1[TS1E]  
GPIO2[TS2E]  
5V tolerant  
3.3V LVTTL  
I/O[O]  
1, 6  
Even Trace execution status. To access this function, software must  
toggle a DCR register bit.  
General Purpose I/O  
or  
GPIO3[TS1O]  
GPIO4[TS2O]  
5V tolerant  
3.3V LVTTL  
I/O[O]  
I/O[O]  
1, 6  
Odd Trace execution status. To access this function, software must  
toggle a DCR register bit.  
General Purpose I/O  
5V tolerant  
3.3V LVTTL  
GPIO5:8[TS3:6]  
GPIO9[TrcClk]  
1
Trace status. To access this function, software must toggle a DCR  
register bit.  
General Purpose I/O  
or  
5V tolerant  
3.3V LVTTL  
I/O[O]  
1
Trace interface clock. A toggling signal that is always half of the CPU  
core frequency. To access this function, software must toggle a DCR  
register bit.  
2.5V CMOS  
w/pull-down  
TestEn  
RcvrInh  
Test Enable.  
I
I
I
Receiver Inhibit. Used only for manufacturing tests. Pull up for normal  
operation.  
5V tolerant  
3.3V LVTTL  
2
2
Driver Inhibit 1 and 2. Used only for manufacturing tests. Pull up for  
normal operation.  
5V tolerant  
3.3V LVTTL  
DrvrInh1:2  
An external clock input than can be used as an alternative to SysClk  
to run the CPU core. Which clock input is used is determined by  
software settings.  
5V tolerant  
3.3V LVTTL  
TmrClk  
I
1
Power  
Ground  
GND  
Note: Pins J9–J12, K9–K12, L9–L12, and M9–M12 are also thermal  
balls.  
AVDD  
OVDD  
VDD  
Filtered voltage input for PLL (analog) circuits  
Output driver voltage—3.3V  
Logic voltage—2.5V  
Other pins  
Connect G19 to GND. Do not connect signals, voltage, or ground to  
any other reserved pins.  
Reserved  
AMCC  
27  
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