Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Signal Description
Data Sheet
Table 9. Add-On Bus General Pins
Signal
Type
Description
SYSRST#
out
System Reset. An active-low buffered PCI bus RST# output signal. The signal is asynchro-
nous and can be asserted through software from the PCI host interface.
BPCLK
ADCLK
IRQ#
out
in
Buffered PCI Clock. This output is a buffered form of the PCI bus clock and has all of the
behavioral characteristics of the PCI clock (i.e., DC-to-33 MHz capability).
Add-On Clock. All internal S5320 Add-On bus logic is synchronous to this clock. The clock
is asynchronous to the PCI bus logic unless connected to the BPCLK signal.
out
in
Interrupt Request. This output signals to Add-On logic that a significant event has occurred
as a result of activity within the S5320.
ADDINT#
Add-On interrupt. When enabled and asserted, this input will cause a PCI bus interrupt by
driving INTA# low. The input is level sensitive and can be driven by multiple sources. This
signal is connected to an internal 50k Ohm pull-up.
FLT#
in
Float. Floats all S5320 output signals when asserted. This signal is connected to an internal
50k Ohm pull-up
Pin 125
Pin 139
Pin 140
Pin 156
Pin 134
X
X
X
X
X
For factory use only. Must be left open. (RSVD1)
For factory use only. Must be left open. (RSVD2)
For factory use only. Must be left open. (RSVD3)
For factory use only. Must be left open. (RSVD4)
For factory use only. Must be left open. (RSVD5)
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DS1656
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