Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
Figure 75. Active Mode 32-Bit PCI Write w/PTWAIT#
3
4
7
8
9
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
01b
PTBE[3:0]#
DXFR#
Data1 Data2
Data3
Data4
Data5
Fh
DQ[31:0]
PTADR#
PTWAIT#
DATA1 DATA2
DATA3
DATA4 DATA5
Clock by Clock description of Figure 75
Clock 5: No data transfer takes place at the rising
edge of clock 5 since the previous cycle was an Add-
On initiated wait state (because PTWAIT# was active
(low) at the rising edge of clock 4). The S5320 asserts
DXFR# and drives the third data onto the DQ bus
since PTWAIT# was inactive (high) at the rising edge
of clock 5. The Add-On device drives PTWAIT# active
(low) requesting a wait state on the next cycle.
Clock 1: The S5320 drives PTATN# and PTBURST#
active (low), indicating the start of a PCI to Add-On
data transfer with more than one data cycle. PTBE[3:0]
and PTNUM[1:0] are driven to their appropriate values
for this transfer. PTWR is driven high indicating a
Pass-Thru write.
Clock 2: Since this region does not have PTADR#
enabled as an output and PTWAIT# is high at the ris-
ing edge of clock 2, the first data transfer is indicated
by driving DXFR# low and the data on the data bus
DQ[31:0] .
Clock 6: DXFR# is sampled active by the Add-On
device which indicates that the Add-On device must
latch the third data word at the rising edge of this
clock. The S5320 drives DXFR# inactive and tri-states
the DQ bus since PTWAIT# was active (low) at the ris-
ing edge of clock 6. The Add-On keeps PTWAIT#
asserted indicating it wants to add a wait state on the
next cycle.
Clock 3: DXFR# is sampled active by the Add-On
device which indicates that the Add-On device must
latch the first data word at the rising edge of this clock.
Valid data is determined by decoding the PTBE[3:0]#
lines. The Add-On device drives PTWAIT# active (low)
requesting a wait state on the next cycle.
Clock 7: No data transfer takes place on the rising
edge of this clock since the previous cycle was an
Add-On initiated wait state (because PTWAIT# was
active (low) at the rising edge of clock 6).
Clock 4: DXFR# is sampled active (low) by the Add-
On device which indicates that the Add-On device
must latch the second data word at this clock edge.
The S5320 tri-states its output bus since PTWAIT#
was inactive (high) at the rising edge of clock 4. Addi-
tionally, the S5320 deasserts DXFR# indicating that no
data transfer will occur on the next clock edge (this is
because this cycle is a wait state since PTWAIT# was
active (low) at the rising edge of clock 4. The Add-On
device deasserts PTWAIT# indicating no wait state on
the next clock.
Clock 8: No data transfer takes place on the rising
edge of this clock since the previous cycle was an
Add-On-initiated wait state (because PTWAIT# was
active (low) at the rising edge of clock 7). DXFR# is
driven active (low) and the fourth data is driven onto
the DQ bus since PTWAIT# was inactive (high) at the
rising edge of clock 8. PTBURST# is driven inactive
(high) indicating that after this data word is transferred,
there is only one data word left to transfer.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
