Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
For all Active mode transfers, the DXFR# signal is
used by Add-On logic as the data transfer signal. Data
must be latched at the rising edge of ADCLK when
DXFR# is asserted for a PCI write. Conversely, for PCI
Reads, the rising edge of ADCLK when DXFR# is
asserted can be used to increment to the next data
field.
The PTADR# signal is controlled by the most signifi-
cant bit of every region control field in the PTCR
register. If this bit is zero then the PTADR# pin is not
driven at the start of an Active mode transfer. If this bit
is set to one, the PTADR# pin will be enabled and
driven active (low) for one and only one clock after
PTATN# was sampled active provided PTWAIT# was
also sampled high.
Figure 70. Active mode PCI Read (Zero Programmed
Wait States) with PTADR#
Figure 72. Active Mode PCI Write without PTADR#
1
2
3
4
5
6
7
1
2
3
4
5
6
7
ADCLK
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
01b
01b
PTBE[3:0]
DXFR#
0h
Fh
PTBE[3:0]
DXFR#
0h
Fh
DQ[31:0]
PTWAIT#
PTADR#
PTADDR
DATA
DQ[31:0]
PTWAIT#
PTADR#
DATA
Figure 71. Active Mode PCI Read without PTADR#
When PTADR# is active (low), the S5320 will drive the
DQ[31:0] bus with the 32-bit PCI address regardless of
the PTMODE pin. To avoid contention on the DQ[31:0]
bus during PCI read cycles, the S5320 incorporates a
turnaround cycle before starting to drive the data
(DXFR# assertion). This is needed only when
PTADR# is enabled and when zero wait states are
programmed during a Pass-Thru read cycle. The cycle
immediately following the address cycle will be a turn-
around cycle as shown in Figure 70.
1
2
3
4
5
6
7
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
01b
0h
PTBE[3:0]
DXFR#
Fh
If PTADR# is disabled, the DXFR# output will be
driven one clock cycle after PTATN# is valid (PTATN#
is not considered active until PTATN# is low and
PTWAIT# is high) regardless of the transfer being a
read or a write. Figure 71 shows a PCI read cycle with
PTADR# disabled.
DQ[31:0]
PTWAIT#
PTADR#
DATA
Figure 72 shows a Pass-Thru write cycle with PTADR#
disabled.
130
DS1656
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