Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
Active mode Programmable Wait States
PTRDY#/PTWAIT#
Bits 0,1,2 of the PTCR register control this feature.
Wait States are programmed on a per region basis.
For example: region one can be set for zero wait
states while other regions may have multiple wait
states programmed.
In Active mode, the PTRDY#/PTWAIT# pin takes the
PTWAIT# function, which is the opposite function of
this pin when configured for passive mode. That is, if
the part is configured to operate in Active mode,
PTWAIT# asserted low means the Add-On wishes to
insert wait states.
Wait state options are 0,1,2,...7 wait states. The S5320
will always count N wait states (N=0,1,..7) before com-
pleting the current data phase.
Add-On peripherals are allowed to insert wait state
cycles at any time during an Active mode transfer.
When PTWAIT# has been sampled low, the S5320 will
tri-state its DQ[31:0] bus in order to allow other Add-
On devices to use the bus without contention.
Figures 76, 77 and 78 show Pass-Thru transfers with
programmed wait states.
Figure 73. Active Mode PCI Write with Add-On Initiated Wait States Using PTWAIT#
3
4
7
8
9
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
01b
0h
PTBE[3:0]#
DXFR#
Fh
DQ[31:0]
PTADR#
PTWAIT#
PTADDR
DATA
Figure 74. Active Mode 32-Bit PCI Write
The address phase of a Pass-Thru consists of the
cycles from PTATN# asserted through PTADR#
asserted (if PTADR# has been programmed to be dis-
abled, there is no address phase). If PTWAIT# is
asserted before the address phase, the address
phase is delayed. The address phase will occur during
the cycle after the clock edge that PTWAIT# is sam-
pled high and PTATN# is sampled low.
1
2
3
4
5
6
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
01b
0h
The data phase(s) of a Pass-Thru consists of all the
cycles after the (possibly nonexistent) address phase.
During data phases, a wait is incurred during the cycle
after PTWAIT# is sampled asserted.
PTBE[3:0]
DXFR#
Fh
Note: If PTWAIT# is activated in order to access other
registers internal to the S5320, the user is responsible
for inserting any needed turnaround cycles in order to
avoid bus contention on the DQ bus.
PTADDR
DQ[31:0]
PTWAIT#
PTADR#
DATA
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
