Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
Clock 9: DXFR# is sampled active (low) by the Add-
On device which indicates that the Add-On device
must latch the fourth data word at the rising edge of
this clock. PTATN# is driven inactive (high) indicating
that this will be the last data phase.
Figure 76 shows a Pass-Thru Burst Write data transfer
in which the S5320 has been programmed to strobe
data using a one-wait state delay. The Add-On device
leaves PTWAIT# inactive (high) for all time.
Clock by Clock description of Figure 76
Clock 10: DXFR# is sampled active (low) by the Add-
On device which indicates that the Add-On device
must latch the fifth data word at the rising edge of this
clock.
Clock 1: The S5320 drives PTATN# and PTBURST#
active (low) indicating the start of a PCI to Add-On
data transfer with more than one data cycle. PTBE[3:0]
and PTNUM[1:0] are driven to their appropriate values
for this transfer. PTWR is driven high indicating a
Pass-Thru write.
DXFR# is deasserted since the access is complete.
PTBE# is driven to Fh indicating all 4 bytes have been
accessed. PTNUM and PTWR may change state
since the access is complete.
Clock 11: PTBE# may change state.
Figure 76. Active Mode PCI Write Showing a One Wait State Programmed Delay
3
4
9
0
1
2
5
6
7
8
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1h
PTBE[3:0]#
DXFR#
Data1
Data2
DATA2
Data3
Data4
Fh
DQ[31:0]
PTADR#
PTWAIT#
DATA1
DATA3
DATA4
PTADDR
134
DS1656
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