Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
Figure 69. PCI to Add-On Passive Read to an 16-bit Add-On Device
3
4
7
8
9
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
3h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
WR#
0h
3h
0h
3h
0h
3h
Fh
2Ch
Ch
3h
Ch
3h
Ch
3h
ADDR
[31:16]
DQ[31:16]
DQ[15:0]
PTADR#
PTRDY#
ADDR
[15:0]
D1
D1
D2
D2
D3
D3
LOW
HIGH
LOW
HIGH
LOW
HIGH
Table 45. Showing Big Endian Conversion for 32-bit
Table 47. Big Endian conversion for an 8-bit bus. The
S5320 drives D[7:0] only
Byte#
PCI Byte
D7-D0
Add-On Byte
D31-D24
D23-D16
D15-D8
PCI Byte
Lane
Add-On Bus
Byte Lane
0
1
2
3
Transfer
1st XFER
2nd XFER
3rd XFER
4th XFER
Byte #
D15-D8
D23-D15
D31-D24
0
1
2
3
D7-D0
D15-D8
D23-D16
D31-D24
D7-D0
D7-D0
D7-D0
D7-D0
D7-D0
Table 46. Big Endian conversion for a 16-bit bus. The
S5320 drives D[15:0] only
In Active mode, wait states can also be programmed.
This enables easier interfacing to slow Add-On logic
whichcannot transferdataatthe fullADCLKspeed.The
S5320 inserts a turnaround cycle after the address
phase for PCI Read cycles. If one or more wait states
have been programmed, the turnaround cycle is con-
sidered the first wait state of the first data phase of that
transaction.
PCI Byte
Lane
Add-On Bus
Byte Lane
Transfer
1st XFER
1st XFER
2nd XFER
2nd XFER
Byte #
0
1
2
3
D7-D0
D15-D8
D23-D16
D31-D24
D15-D8
D7-D0
D15-D8
D7-D0
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DS1656
129
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
