Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
Figure 77. 16-Bit Active Mode PCI Read w/ Programmed Wait States
3
4
9
14
7
8
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1h
PTBE[3:0]#
DXFR#
Ch
3h
Fh
DQ[15:0]
PTADR#
PTWAIT#
PTADDR
LOW
HIGH
Clock 2: Since this region does have PTADR#
enabled as an output, it is driven active (low) and the
PCI address for the current transaction is presented
on the DQ[31:0] bus.
Clock 6: DXFR# is asserted indicating that data will be
transferred on the next rising clock edge (clock 7).
DATA2 is driven onto the DQ[31:0] bus.
Clock 7: The Add-On side device latches the second
Clock 3: The Add-On device must latch the PCI
data word (DATA2) at the rising edge of this clock.
address at the rising edge of this clock.
Clock 8: DXFR# is asserted indicating that data will be
transferred on the next rising clock edge (clock 9).
DATA3 is driven onto the DQ[31:0] bus. PTBURST# is
driven inactive indicating that after this data word is
transferred, there is only one data word left to transfer.
Clock 4: DXFR# is asserted low indicating that data
will be transferred on the next rising clock edge (clock
5). Data1 is driven onto the DQ[31:0] bus.
Clock 5: The Add-On device must latch the first data
word at the rising edge of this clock. Valid data is
determined by decoding the PTBE[3:0]# lines.
Clock 9: The Add-On side device latches the third
data word (DATA3) at this clock edge.
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
