Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
Figure 68. PCI to Add-On Passive Write to an 8-bit
3
4
7
8
9
0
1
2
5
6
10
11
12
13
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
0h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
RD#
0h
1h
3h
7h
0h
8h
Ch
Eh
Fh
2Ch
Eh
Dh
Bh
7h
7h
Bh
Dh
Eh
ADD[7:0]
DQ[7:0]
30h
9Ah
D4h
08h
AAh
BBh
CCh
DDh
ADD[31:8]
DQ[31:8]
PTADR#
PTRDY#
Clock 5: The Add-On logic latches BYTE1. RD# and
BE2# are sampled asserted by the S5320, so BYTE2
of the APTD is driven on DQ[7:0] and PTBE2# is deas-
serted. The Add-On device asserts RD# and BE3#,
thus requesting that BYTE3 of the APTD be driven on
the DQ bus during the next cycle. PTRDY# is also
asserted, indicating that the transfer is complete.
is driven on DQ[7:0] and PTBE3# is deasserted. The
Add-On device asserts RD# and BE2#, thus request-
ing that BYTE2 of the APTD be driven on the DQ bus
during the next cycle.
Clock 8: The Add-On logic latches BYTE3 of the sec-
ond DWORD. RD# and BE2# are sampled asserted
by the S5320, so BYTE2 of the APTD is driven on
DQ[7:0] and PTBE2# is deasserted. The Add-On
asserts RD# and BE1#, thus requesting that BYTE1 of
the APTD be driven on the DQ bus during the next
cycle.
Clock 6: The Add-On logic latches BYTE2. RD# and
BE3# are sampled asserted by the S5320, so BYTE3
of the APTD is driven on DQ[7:0]. PTRDY# is sampled
asserted, so the previous transfer is complete. The
PTBE# signals are updated to indicate which bytes are
valid for the next transfer (in this case, all bytes are
valid for the second DWORD, so PTBE# = 0h). The
S5320 deasserts PTBURST#, as it only has one
DWORD left to transfer. The Add-On device asserts
RD# and BE3#, thus requesting that BYTE3 of the
second DWORD in the APTD be driven on the DQ bus
during the next cycle.
Clock 9: The Add-On logic latches BYTE2 of the sec-
ond DWORD. RD# and BE1# are sampled by the
S5320, so BYTE1 of the APTD is driven on DQ[7:0]
and PTBE1# is deasserted. The Add-On asserts RD#
and BE0#, thus requesting that BYTE0 of the APTD be
driven on the DQ bus during the next cycle. PTRDY#
is also asserted, indicating that the transfer is com-
plete. As PTBURST# is already deasserted, the Add-
On recognizes that this is the last transfer.
Clock 7: The Add-On logic latches BYTE3 of the first
DWORD. RD# and BE3# are sampled asserted by the
S5320, so BYTE3 of the second DWORD in the APTD
Clock 10: The Add-On logic latches BYTE1 of the
second DWORD. RD# and BE0# are sampled by the
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127
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
