Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
cycle decodes to one of the S5320 Pass-Thru regions,
DEVSEL# is asserted. If the Pass-Thru logic is cur-
rently idle (not busy finishing a previous Pass-Thru
operation), the bus cycle type is decoded and the Add-
On Pass-Thru status outputs are set to initiate a trans-
fer on the Add-On bus. The following sections
describe the behavior of the PCI interface for Pass-
Thru accesses to the S5320. Single cycle accesses,
burst accesses, and target-initiated retries are
detailed.
burst access, the Pass-Thru status indicators notify
the Add-On logic.
For Pass-Thru burst writes, the S5320 responds
immediately (asserting TRDY#). The S5320 transfers
the first data phase of the burst into the FIFO, and
stores the PCI address in the Pass-Thru Address Reg-
ister (APTA). The S5320 can accept up to 8 DWORDs
from the PCI bus before transferring one DWORD on
the Add-On side. If the Add-On bus is slow, the device
will keep the FIFO full until the data is ready to be
transferred by the slow Add-On bus. If the Add-On bus
is fast at accepting the data, then the FIFO will con-
tinue an indefinite burst, or until the PCI master is
forced to relinquish the bus for arbitration reasons, or
the PCI bus master has gone beyond the Pass-Thru
region address space. For burst accesses, the APTA
is automatically incremented by the S5320 for each
data phase.
PCI Pass-Thru Single Cycle Accesses
A single cycle transfer is the simplest of PCI bus trans-
actions. Single cycle transfers have an address phase
and a single data phase. The PCI bus transaction
starts when an initiator drives address and command
information onto the PCI bus and asserts FRAME#.
The initiator always deasserts FRAME# before the last
data phase. For single cycle transfers, FRAME# is
only asserted during the address phase (indicating the
first data phase is also the last).
For Pass-Thru burst reads, the S5320 claims the PCI
cycle (asserting DEVSEL#). The request for data is
passed on to Add-On logic and the PCI address is
stored in the APTA register. The device will prefetch
data if the feature is enabled. The S5320 then drives
the requested data on the PCI bus and asserts TRDY#
to begin the next data phase. The APTA register is
automatically incremented by the S5320 after each
data phase.
When the S5320 sees FRAME# asserted, it samples
the address and command information to determine if
the bus transaction is intended for it. If the address is
within one of the defined Pass-Thru regions or internal
PCI Operation Register, the S5320 accepts the trans-
fer (asserts DEVSEL#), and stores the PCI address in
the Pass-Thru Address Register (APTA).
PCI Disconnect Conditions
For Pass-Thru writes, the S5320 responds immedi-
ately (asserting TRDY#) and transfers the data from
the PCI bus into the write FIFO as long as the write
FIFO is not full. The S5320 then indicates to the Add-
On interface that a Pass-Thru write is taking place and
waits for Add-On logic to complete the transfer. Once
the S5320 has captured the data from the PCI bus, the
transfer is finished from the PCI bus perspective, and
the PCI bus becomes available for other transfers.
Before discussing what causes the S5320 to issue a
disconnect on the PCI bus, it might be useful to distin-
guish between a disconnect and retry. A retry occurs
when a PCI initiator does not receive a single TRDY#,
but is issued a STOP# instead. In this case, no data is
transferred. The PCI 2.1 spec states that the initiator is
required to come back and complete this transfer. A
disconnect occurs after at least one data phase was
completed (TRDY# and IRDY# asserted simulta-
neously). This occurs when a STOP# is asserted
either with a TRDY# or after a TRDY#/IRDY# transfer.
In this case, the initiator is not required to return to
complete the transfer.
For Pass-Thru reads, the S5320 indicates to the Add-
On interface that a Pass-Thru read is taking place and
waits for Add-On logic to complete the cycle. If the
Add-On cannot complete the cycle quickly enough, the
S5320 requests a retry from the initiator. The S5320
will fetch one DWORD from the Add-On side, and
store it in the Read FIFO.
In some applications, Add-On logic may not be able to
respond to Pass-Thru accesses quickly. In this situa-
tion, the S5320 will Retry the cycle on the PCI side.
For PCI write cycles, the S5320 will accept up to 8
DWORDs without a disconnect or until the FIFO is full.
For a PCI read cycle, the first access needs to take
less than 16 PCI clocks, otherwise the device will
issue a Retry. A subsequent read transfer must take
less than 8 PCI clocks, otherwise the device will issue
a disconnect.
PCI Pass-Thru Burst Accesses
For PCI Pass-Thru burst accesses, the S5320 cap-
tures the PCI address and determines if it falls into one
of the defined Pass-Thru regions. Accesses that fall
into a Pass-Thru region or internal PCI Operation Reg-
ister are accepted by asserting DEVSEL#. The S5320
monitors FRAME# and IRDY# on the PCI bus to iden-
tify burst accesses. If the PCI initiator is performing a
AMCC Confidential and Proprietary
DS1656
113
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
