Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
Figure 61. PCI To Add-On Passive Write
PTWR and PTBE[3:0] will update on the next rising
edge of ADCLK.
0
1
2
3
4
5
Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1h
PTATN# Asserted. Indicates Pass-Thru access is
pending.
PTBE[3:0]
SELECT#
ADR[6:2]
BE[3:0]#
RD#
0h
Fh
PTBURST# Not asserted. The access has a single
data phase.
PTNUM[1:0] 1h. Indicates the access is to Pass-Thru
region 1.
2Ch
0h
PTWR Asserted. The Pass-Thru access is a write.
PTBE[3:0]# 0h. Indicate the Pass-Thru has all bytes
valid.
DQ[31:0]
PTRDY#
PTDATA
Clock 2: The PTADR# input is asserted to read the
Pass-Thru Address Register. The assertion of
PTADR# will immediately cause the address to be
driven on the DQ bus. RD#, SELECT#, byte enable,
and the address inputs are asserted to read the Pass-
Thru Data Register at offset 2Ch. DQ[31:0] is driven
one clock after RD# and SELECT# are asserted.
Asserting PTADR# and RD# at the same time will save
a clock cycle, since the assertion of the RD# won’t
cause the data to be driven until a clock later. The
Add-On also asserts PTRDY#, indicating that the cur-
rent transfer is complete.
Figure 62. PCI To Add-On Passive Write w/Pass-Thru
Address
0
1
2
3
4
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
Clock 3: PTBE[3:0] are updated to indicate which
bytes have not yet been read. Data is driven on the
DQ bus because RD# was asserted a clock earlier.
The Add-On logic reads the data and deasserts
PTRDY#. As PTRDY# was sampled asserted,
PTATN# is immediately deasserted and the Pass-Thru
access is completed with the next clock. If add-on
logic requires more time to read the Pass-Thru Data
Register (slower memory or peripherals), PTRDY#
can be delayed, extending the cycle.
1h
PTBE[3:0]
SELECT#
0h
Fh
ADR[6:2]
BE[3:0]#
RD#
2Ch
0h
Clock 4: As PTATN# is deasserted, the Pass-Thru
access is complete, and the S5320 can accept new
Pass-Thru accesses starting on the next clock. The
other Pass-Thru signals can also change (in anticipa-
tion of a new transfer). The S5320 stops driving the
DQ bus as RD# and SELECT# were not valid on the
previous cycle.
DQ[31:0]
PTADR#
PTRDY#
A DDR
DATA
Single-Cycle PCI to Pass-Thru Read
Clock 0: The address is recognized as a PCI write to
Pass-Thru region 1. The PCI bus write address is
stored in the Pass-Thru Address Register. The PCI
bus write data is stored in the S5320 Write FIFO. Add-
On bus signals PTATN#, PTBURST#, PTNUM[1:0],
A single-cycle PCI to Pass-Thru read operation occurs
when a PCI initiator reads a single value from a Pass-
Thru region. PCI single cycle transfers consists of an
116
DS1656
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