Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
Figures 58 and 59 show basic operation register
access timing relationships. Detailed AC timings are in
Electrical and AC Characteristics. Chapter 10.
S5320 16-bit Mode Register Accesses
In the S5320 there are two methods of defining the
Add-On DQ width: one is by using the DQMODE pin
and the other is to define a Pass-Thru region size of 8,
16 or 32 bits. The DQMODE pin allows external 16-bit
devices to access S5320 Operation Registers without
additional logic. The external device is able to write
and read the S5320 32-bit registers in two 16-bit cycle
accesses. When performing an Operation Register
access with the DQMODE pin set for 16 bits
(DQMODE = 1), only the lower half (DQ[15:0]) of the
DQ bus is driven during a read or write. The S5320
internally steers the data bus and the byte enables
based on the BE3# input. It is important to note that
the DQMODE pin has no effect on accesses to the
Pass-Thru Data Register. For non 32-bit Pass-Thru
regions, the region size should be used instead. In 16-
bit mode, a 32-bit DWORD write is performed in two
cycles:
For reads (Figure 58), data is driven onto the DQ bus
on the ADCLK cycle after RD# is sampled asserted.
When RD# is not asserted, the DQ outputs float. The
address, byte enable, and RD# inputs must meet
setup and hold times relative to the rising edge of
ADCLK.
For writes (Figure 59), data is clocked into an opera-
tion register on the rising edge of ADCLK in which
WR# is sampled asserted. Address, byte enables,
WR# and data must all meet setup and hold times rel-
ative to the rising edge or ADCLK.
Figure 58. Read Operation Register
ADCLK
SELECT#
Cycle 1: DQ[15:0] is driven with the lower-WORD.
WR#, ADR and SELECT# are asserted, BE[1:0]# indi-
cates which bytes of the WORD are valid, and BE3#
(which has been redefined as ADR1 when in 16-bit
mode) is set to zero, indicating that the write is for the
lower-WORD of the DWORD transfer. DQ[15:0] will be
written to the bottom 16 bits of the internal 32-bit regis-
ter (be it a Mailbox, Pass-Thru configuration register,
etc.).
ADR[6:2]
BE[3:0]#
RD#
VALID
VALID
DQ[31:0]
VALID
Cycle 2: DQ[15:0] is driven with the upper-WORD.
WR#, ADR and SELECT# are asserted, BE[1:0]# indi-
cate which bytes of the WORD are valid, and BE3# is
set to one, indicating that the write is for the upper-
WORD of the DWORD transfer. DQ[15:0] will be writ-
ten to the upper 16-bits of the internal 32-bit register.
Figure 59. Write Operation Register
ADCLK
SELECT#
ADR[6:2]
BE[3:0]#
WR#
VALID
VALID
Transfered
DQ[31:0]
DATA
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
