Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
With many devices, particularly memories, the first
access takes longer than subsequent accesses
(assuming they are sequential and not random). For
this reason, the PCI specification allows 16 clocks to
respond to the first data phase of a PCI cycle and 8
clocks for subsequent data phases (in the case of a
burst) before a retry/disconnect is issued by the
S5320.
Add-On cannot complete the access within 16 clocks,
a retry is requested (STOP# asserted without data
transfer). If the Add-On manages to complete the data
transfer into the PT Read FIFO, but after a retry was
issued, the data is held in the FIFO until the original
master comes back to read it. All subsequent PCI
accesses to a Pass-Thru address other than the one
corresponding to the data in the FIFO will be termi-
nated with a PCI retry. Only a PCI access with a
matching address can access the data in the PT Read
FIFO, and thus release the Pass-Thru region for other
accesses.
The S5320 also requests a disconnect if an initiator
attempts to burst past the end of a Pass-Thru region.
The S5320 updates the Pass-Thru Address Register
(APTA) for each data phase during bursts, and if the
updated address is not within the current Pass-Thru
region, a disconnect is issued. Accesses to undefined
addresses will cause the PCI host to receive a Master
Abort cycle (no DEVSEL# is asserted by the S5320).
If the Add-On is busy performing a Pass-Thru write
operation when a PCI read occurs, the S5320
requests an immediate retry. If the Add-On is busy per-
forming a Pass-Thru read operation when another PCI
read occurs, the S5320 determines whether the read
is a retry from a previous access, and if so, attempts to
continue the read where it left off. If the address is
non-sequential, the new access is issued a retry. This
allows the PCI bus to perform other operations. S5320
PCI Operation Registers may be accessed while the
Add-On is still completing a Pass-Thru access. Only
other Pass-Thru region accesses receive retry
requests.
For example, a PCI system may map a 512 byte Pass-
Thru memory region to 0DC000h to 0DC1FFh. A PCI
initiator attempts a four DWORD burst with a starting
address of 0DC1F8h. The first and second data
phases complete (filling the DWORDs at 0DC1F8h
and 0DC1FCh), but the third data phase causes the
S5320 to issue a disconnect. This forces the initiator to
present the address 0DC200h on the PCI bus. If this
address is part of another S5320 Pass-Thru region,
the device accepts the access, but if not, a Master
Abort cycle occurs.
If the prefetch feature is enabled, the Pass-Thru inter-
face will prefetch data, which should improve the
performance on subsequent cycles to the same
region. In the event that the Add-On cannot prefetch
the first data before the S5320 issues a PCI retry, the
prefetched data will be held in the read FIFO until the
original master comes back to request it. Other PCI
read requests to the Pass-Thru region will be termi-
nated with immediate Retries.
PCI Write Disconnect
When the S5320 issues a disconnect for a PCI Pass-
Thru write, it indicates that the Add-On is still complet-
ing a previous non-sequential Pass-Thru access or the
FIFO is full. If the incoming access is a continuation of
a previous one, no disconnect is issued and the trans-
action can continue where it left off (perhaps due to a
previous disconnect or master time-out). PCI Opera-
tion Registers may be accessed while the Add-On is
still completing a Pass-Thru access. Only Pass-Thru
region accesses receive disconnect requests.
If the prefetch feature is disabled, a PCI read cycle is
not completed until the data is first transferred from the
Add-On bus into the PT Read FIFO. The device will
not prefetch, but will only request data from the Add-
On bus after the PCI bus has requested the data.
Pass-Thru bursts will not be performed in this case. In
the event that a non-prefetchable Add-On cannot pro-
vide the second (or third, or fourth...) data to the PCI
read request within the PCI Target Subsequent
Latency period (eight PCI clocks), the S5320 will issue
a PCI disconnect (STOP# asserted with data transfer).
If the Add-On manages to transfer the second (or
third, or fourth...) data to the PT Read FIFO, but after
the disconnect, the data may be held in the FIFO until
the original master comes back to read it. Depending
upon the setting of the Retry Flush Enb bit, the data is
held in the FIFO, and all other PCI read requests will
be terminated with immediate Retries.
PCI Read Disconnect
If the S5320 issues a disconnect for a PCI Pass-Thru
read, this indicates that the Add-On could not com-
plete the read in the required time (16 clocks for the
first data phase, 8 PCI clocks for the 2nd or later data
phases).
When the PCI performs a read to a Pass-Thru region,
the Add-On device must complete a Pass-Thru data
transfer by writing the appropriate data into the Pass-
Thru Data FIFO (APTD). If the Add-On can perform
this before the required time (see above), the S5320
asserts TRDY# to complete a PCI read transfer. If the
114
DS1656
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
