Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
MAILBOX OVERVIEW
Data Sheet
READ FIFO OVERVIEW
For a detailed description of the Mailbox interface, ref-
erence previous Mailbox Overview section.
The S5320 has an 8x32-bit Read FIFO, which allows
data to be prefetched from the add on bus. The user
can program the device to prefetch 2,4 or 8 DWORDs
for each region or disable prefetching completely. For
the first PCI read cycle, the device will request data
from the Add-On bus. As the PCI bus reads the FIFO,
and until after the PCI transfer has finished, the S5320
will prefetch the next N (2, 4 or 8) DWORDs from the
Add-On. The prefetched data is valid as long as the
PCI read addresses are sequential. If the current PCI
read address is not the previous address plus four, or
if a PCI write access occurs, the S5320 will flush the
FIFO and start a new transfer at this address. Flushing
the FIFO will incur a minimum loss of one PCI clock
cycle or possibly more if the Add-On logic has not fin-
ished its current prefetching transfer. Note that
prefetching is not performed past the upper limit of the
base address region. In fact, prefetching is disabled
when the PCI address is eight DWORDs from the end
of the region.
PASS-THRU OVERVIEW
The S5320 provides data transfers between the PCI
bus and the user local bus through the Pass-Thru data
channel. Using a handshaking protocol with Add-On
device(s), the PCI bus can directly access data on the
Add-On bus and internal S5320 Operation registers.
The Pass-Thru data channel is very flexible for user
memory access or accessing registers within peripher-
als on the Add-On bus. Pass-Thru operation in Active
or Passive mode requires an external non-volatile
memory device to define and configure the Pass-Thru
channel region sizes and bus widths.
Four user-configurable Pass-Thru regions are avail-
able in the S5320. Each region is defined by a PCI
Configuration Base Address Register (BADR1-4). A
Pass-Thru region defines a block of predefined user
space address in either host memory or I/O areas.
Memory mapped regions can be requested below 1
Mbyte (Real Mode address space for a PC). Each
region is configurable for bus widths of 8, 16 or 32 bits
for the Add-On bus interface.
Prefetch cycles are always 32 bits regardless of Add-
On bus width or the byte enables requested by the
PCI.
FUNCTIONAL DESCRIPTION
The S5320 Pass-Thru channel supports single data
transfers as well as burst transfers. When accessed
with burst transfers, the S5320 supports data transfers
at the full PCI bandwidth. The data transfer rate is only
limited by the PCI initiator performing the access and
the speed of the Add-On bus logic.
The S5320 Pass-Thru interface supports both single
cycle (one data phase) and burst accesses (multiple
data phases).
Pass-Thru Transfers
The Pass-Thru interface offers two different modes of
operation: Passive mode and Active mode. Passive
mode is configured by strapping the pin PTMODE
high, while Active mode is configured by strapping the
pin PTMODE Low.
WRITE FIFO OVERVIEW
For PCI write cycles, the S5320 has an 8x32-bit Write
FIFO to increase performance for slow Add-On
devices. When the FIFO is enabled, the S5320 will
accept data transfers from the PCI bus at zero wait
states until the FIFO is full. The device continues to fill
the FIFO as long as the transfers are sequential. The
S5320 can continue accepting sequential write PCI
transfers as long as the FIFO is not full and the bound-
ary of the Pass-Thru region defined by the Base
Address Register is not crossed. If the next data
access is for a non-sequential address, the FIFO must
first be emptied by the Add-On peripheral in order for
the next transfer to occur.
PTMODE = 1 - Passive Operation
PTMODE = 0 - Active Operation
Passive operation allows external Add-On bus periph-
erals to provide read and write control signals to the
S5320. The user drives SELECT#, RD#, WR#.
ADR[6:2] and PTRDY#. The Add-On bus logic has the
flexibility of determining when it wants to perform
reads/writes.
Some applications may require that a PCI address be
passed for Pass-Thru accesses. For example, a 4-
Kbyte Pass-Thru region on the PCI bus may corre-
spond to a 4-Kbyte block of SRAM on the Add-On
card. If a PCI initiator accesses this region, the Add-
On would need to know the offset within the memory
device to access. The Pass-Thru Address Register
(APTA) allows Add-On logic to access address infor-
The Write FIFO can be disabled, thus configuring the
FIFO to act as a single DWORD data buffer. In this
case, PCI Write Posting is not possible.
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