Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Pass-Thru Operation
Data Sheet
address phase followed by a single data phase. If the
S5320 determines that the address is within one of its
defined Pass-Thru regions, it indicates to the Add-On
a write to the Pass-Thru Data Register (APTD) is
required.
PTBURST# Deasserted. The access has a single data
phase.
PTNUM[1:0] 2h. Indicates the access is to Pass-Thru
region 2.
PTWR Deasserted. The Pass-Thru access is a read.
Figure 63 shows a Passive Mode single cycle Pass-
Thru read access (Add-On write) using PTADR#. The
Add-On reads data from a source on the Add-On and
writes it to the APTD register.
PTBE[3:0]# 0h. Indicates the Pass-Thru access has all
bytes valid.
Clock 2: The PTADR# input is asserted to read the
Pass-Thru Address Register. The address can be
latched on the next rising-edge of ADCLK.
Figure 63. PCI To Add-On Passive Read
Clock 3: This turn-around cycle is required to avoid
contention on the DQ bus. Time must be allowed after
PTADR# is deasserted for the DQ outputs to float
before add-on logic attempts to write to the Pass-Thru
Read FIFO.
0
1
2
3
4
5
6
ADCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
Clock 4: WR#, SELECT#, BE[3:0]#, and ADR[6:2] are
asserted to write to the Pass-Thru Read FIFO at
address 2Ch. The Add-On logic drives the DQ bus
with the requested data. PTRDY# is also asserted,
indicating that the Add-On is finished with the transfer.
2h
PTBE[3:0]
SELECT#
ADR[6:2]
BE[3:0]#
WR#
0h
Fh
Clock 5: The data on the DQ bus is latched into the
Pass-Thru Read FIFO. As the S5320 samples
PTRDY# asserted, PTATN# is deasserted and the
Pass-Thru access is complete. PTBE[3:0] will update
one clock after WR# is asserted to indicate which
bytes have not yet been read. If add-on logic requires
more time to provide data (slower memory or peripher-
als), PTRDY# can be delayed, extending the cycle.
2Ch
0h
DQ[31:0]
PTRDY#
PTADR#
ADDR
DATA
Clock 6: As PTATN# is deasserted, the Pass-Thru
access is complete, and the S5320 can accept new
Pass-Thru accesses starting on the next clock. The
other Pass-Thru signals can also change (in anticipa-
tion of a new transfer).
PCI to Pass-Thru Burst Writes
Clock 0: The address is recognized as a PCI read of
Pass-Thru region 2. The PCI bus read address is
stored in the Pass-Thru Address Register. Add-On bus
signals PTATN#, PTBURST#, PTNUM[1:0], PTWR
and PTBE[3:0] will update on the next rising edge of
ADCLK.
A PCI to Pass-Thru burst write operation occurs when
a PCI initiator writes multiple values to a Pass-Thru
region. A PCI burst cycle consists of an address phase
followed by multiple data phases. If the S5320 deter-
mines that the requested address is within one of its
defined Pass-Thru regions, the initial PCI address is
stored into the Pass-Thru Address Register (APTA).
The data from each data-cycle is individually latched
into the Pass-Thru Data register (APTD) or Pass-Thru
Write FIFO.
Clock 1: Pass-Thru signals PTATN#, PTBURST#,
PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-
cate what action is required by Add-On logic. These
status signals are valid only when PTATN# is active.
Add-On logic can decode status signals upon the
assertion of PTATN#.
PTATN# Asserted. Indicates a Pass-Thru access is
pending.
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