MAX 9000 Programmable Logic Device Family Data Sheet
The programming times described in Tables 7 through 9 are associated
with the worst-case method using the ISP algorithm.
Table 7. MAX 9000 tPULSE & CycleTCK Values
Device
Programming
Stand-Alone Verification
tVPULSE (s) CycleVTCK
tPPULSE (s)
CyclePTCK
EPM9320
11.79
2,966,000
0.15
1,806,000
EPM9320A
EPM9400
EPM9480
12.00
12.21
12.42
3,365,000
3,764,000
4,164,000
0.15
0.15
0.15
2,090,000
2,374,000
2,658,000
EPM9560
EPM9560A
Tables 8 and 9 show the in-system programming and stand alone
verification times for several common test clock frequencies.
Table 8. MAX 9000 In-System Programming Times for Different Test Clock Frequencies
Device
fTCK
Units
10 MHz 5 MHz 2 MHz
1 MHz 500 kHz 200 kHz 100 kHz 50 kHz
EPM9320
12.09
12.38
13.27
14.76
17.72
26.62
41.45
71.11
s
EPM9320A
EPM9400
EPM9480
12.34
12.59
12.84
12.67
12.96
13.26
13.68
14.09
14.50
15.37
15.98
16.59
18.73
19.74
20.75
28.83
31.03
33.24
45.65
49.85
54.06
79.30
87.49
95.70
s
s
s
EPM9560
EPM9560A
Table 9. MAX 9000 Stand-Alone Verification Times for Different Test Clock Frequencies
Device
fTCK
1 MHz 500 kHz 200 kHz 100 kHz 50 kHz
Units
10 MHz 5 MHz 2 MHz
EPM9320
0.33
0.52
1.06
1.96
3.77
9.18
18.21
36.27
s
EPM9320A
EPM9400
EPM9480
0.36
0.39
0.42
0.57
0.63
0.69
1.20
1.34
1.48
2.24
2.53
2.81
4.33
4.90
5.47
10.60
12.02
13.44
21.05
23.89
26.73
41.95
47.63
53.31
s
s
s
EPM9560
EPM9560A
22
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
