MAX 9000 Programmable Logic Device Family Data Sheet
The output buffer in each IOC has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slower slew
rate reduces board-level noise and adds a nominal timing delay to the
output buffer delay (tOD) parameter. The fast slew rate should be used for
speed-critical outputs in systems that are adequately protected against
noise. Designers can specify the slew rate on a pin-by-pin basis during
design entry or assign a default slew rate to all pins on a global basis. The
slew rate control affects both rising and falling edges of the output signals.
Table 6. Peripheral Bus Sources
Peripheral Control
Signal
Source
EPM9400 EPM9480
EPM9320
EPM9560
EPM9320A
EPM9560A
OE0/ENA0
OE1/ENA1
OE2/ENA2
OE3/ENA3
OE4/ENA4
OE5
Row C
Row B
Row A
Row B
Row A
Row D
Row C
Row B/GOE
Row E
Row F
Row G
Row F
Row E
Row F
Row E
Row E
Row E
Row B
Row A
Row D
Row C
Row B/GOE
Row B
Row B
Row A
Row A
Row D
Row C
Row B/GOE
Row D
Row C
Row B/GOE
OE6
OE7/CLR1
CLR0/ENA5
CLK0
Row A/GCLR Row A/GCLR Row A/GCLR Row A/GCLR
GCLK1
GCLK2
Row D
Row C
GCLK1
GCLK2
Row D
Row C
GCLK1
GCLK2
Row D
Row C
GCLK1
GCLK2
Row D
Row C
CLK1
CLK2
CLK3
The MAX 9000 device architecture supports the MultiVolt I/ O interface
feature, which allows MAX 9000 devices to interface with systems of
differing supply voltages. The 5.0-V devices in all packages can be set for
3.3-V or 5.0-V I/ O pin operation. These devices have one set of VCC pins
for internal operation and input buffers (VCCINT), and another set for I/ O
output drivers (VCCIO).
Output
Configuration
The VCCINTpins must always be connected to a 5.0-V power supply.
With a 5.0-V VCCINT level, input voltages are at TTL levels and are
therefore compatible with 3.3-V and 5.0-V inputs.
18
Altera Corporation
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