MAX 9000 Programmable Logic Device Family Data Sheet
Figure 11. MAX 9000 JTAG Waveforms
TMS
TDI
tJCP
tJCH
tJCL
tJPH
tJPSU
TCK
TDO
t
tJPXZ
tJPCO
JPZX
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSXZ
tJSZX
Signal
to Be
Driven
Table 13 shows the JTAG timing parameters and values for MAX 9000
devices.
Table 13. JTAG Timing Parameters & Values for MAX 9000 Devices
Symbol
Parameter
Min Max Unit
tJCP
TCKclock period
TCKclock high time
TCKclock low time
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCH
tJCL
50
tJPSU
tJPH
JTAG port setup time
20
JTAG port hold time
45
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output
25
25
25
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
20
45
Capture register hold time
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
25
25
25
For detailed information on JTAG operation in MAX 9000 devices, refer to
Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices).
f
Altera Corporation
25
ALTERA [ ALTERA CORPORATION ]
