MAX 7000 Programmable Logic Device Family Data Sheet
Table 32. EPM7192S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-10
Min Max Min Max Min Max
Unit
-7
-15
tCL
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
3.0
1.0
1.8
4.0
2.0
3.0
5.0
4.0
4.0
ns
ns
ns
ns
ns
ns
ns
tASU
tAH
tACO1
tACH
tACL
tCPPW
C1 = 35 pF
7.8
10.0
15.0
3.0
3.0
3.0
4.0
4.0
4.0
6.0
6.0
6.0
Minimum pulse width for clear (2)
and preset
tODH
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
ns
tCNT
fCNT
Minimum global clock period
8.0
8.0
10.0
10.0
13.0
13.0
ns
Maximum internal global clock (4)
frequency
125.0
100.0
76.9
MHz
tACNT
fACNT
Minimum array clock period
ns
Maximum internal array clock (4)
frequency
125.0
166.7
100.0
125.0
76.9
MHz
fMAX
Maximum clock frequency
(5)
100.0
MHz
Table 33. EPM7192S Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-10
Unit
-7
-15
Min Max Min Max Min Max
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.3
0.3
3.2
4.2
1.2
3.1
3.1
0.9
0.5
1.0
5.5
4.0
4.5
9.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
7.0
6.0
7.0
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tFIN
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
tOD2
tOD3
tZX1
tZX2
tZX3
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
46
Altera Corporation
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