MAX 7000 Programmable Logic Device Family Data Sheet
Table 30. EPM7160S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-15
tACNT
fACNT
Minimum array clock period
6.7
8.2
10.0
13.0
ns
Maximum internal array clock (4)
frequency
149.3
166.7
122.0
166.7
100.0
125.0
76.9
MHz
fMAX
Maximum clock frequency
(5)
100.0
MHz
Table 31. EPM7160S Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-15
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.2
0.2
2.6
3.6
1.0
2.8
2.8
0.7
0.4
0.9
5.4
4.0
4.5
9.0
4.0
0.3
0.3
3.2
4.3
1.3
3.4
3.4
0.9
0.5
1.0
5.5
4.0
4.5
9.0
4.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
2.0
2.0
2.0
8.0
1.0
6.0
6.0
3.0
4.0
5.0
8.0
6.0
7.0
10.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tFIN
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
tOD2
tOD3
tZX1
tZX2
tZX3
tXZ
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
C1 = 5 pF
tSU
1.0
1.6
1.9
1.2
2.0
2.2
2.0
3.0
3.0
4.0
4.0
2.0
tH
Register hold time
tFSU
Register setup time of fast
input
tFH
Register hold time of fast
input
0.6
0.8
0.5
1.0
ns
tRD
Register delay
1.3
1.0
2.9
2.8
2.0
1.6
1.3
3.5
3.4
2.4
2.0
2.0
5.0
5.0
1.0
1.0
1.0
6.0
6.0
1.0
ns
ns
ns
ns
ns
tCOMB
tIC
Combinatorial delay
Array clock delay
Register enable time
Global control delay
tEN
tGLOB
44
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