MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more
information on switching waveforms.
(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t
parameter
LPA
must be added to this minimum width if the clear or reset signal incorporates the t
parameter into the signal
LAD
path.
(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4) These parameters are measured with a 16-bit loadable, enabled, up/ down counter programmed into each LAB.
(5) The f
values represent the highest frequency for pipelined data.
MAX
(6) Operating conditions: V
= 3.3 V ± 10% for commercial and industrial use.
CCIO
(7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8) The t
parameter must be added to the t
, t
, t , t , t
, t
, and t
parameters for macrocells
LPA
LAD LAC IC EN SEXP ACL
CPPW
running in the low-power mode.
Tables 30 and 31 show the EPM7160S AC operating conditions.
Table 30. EPM7160S External Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-7 -10
Min Max Min Max Min Max Min Max
Unit
-6
-15
tPD1
tPD2
Input to non-registered output C1 = 35 pF
6.0
6.0
7.5
7.5
10.0
10.0
15.0
15.0
ns
ns
I/O input to non-registered
output
C1 = 35 pF
tSU
tH
Global clock setup time
Global clock hold time
3.4
0.0
2.5
4.2
0.0
3.0
7.0
0.0
3.0
11.0
0.0
ns
ns
ns
tFSU
Global clock setup time of fast
input
3.0
tFH
Global clock hold time of fast
input
0.0
0.0
0.5
0.0
ns
tCO1
tCH
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
C1 = 35 pF
3.9
6.4
4.8
7.9
5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.0
3.0
0.9
1.7
3.0
3.0
1.1
2.1
4.0
4.0
2.0
3.0
5.0
5.0
4.0
4.0
tCL
tASU
tAH
tACO1
tACH
tACL
tCPPW
C1 = 35 pF
10.0
15.0
3.0
3.0
2.5
3.0
3.0
3.0
4.0
4.0
4.0
6.0
6.0
6.0
Minimum pulse width for clear (2)
and preset
tODH
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
1.0
ns
tCNT
fCNT
Minimum global clock period
6.7
8.2
10.0
13.0
ns
Maximum internal global clock (4)
149.3
122.0
100.0
76.9
MHz
frequency
Altera Corporation
43
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