MAX 7000 Programmable Logic Device Family Data Sheet
Table 26. EPM7064S External Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-6 -7
Min Max Min Max Min Max Min Max
Unit
-5
-10
tAH
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
1.8
2.1
2.0
3.0
ns
ns
ns
ns
ns
tACO1
tACH
tACL
tCPPW
C1 = 35 pF
5.4
6.7
7.5
10.0
2.5
2.5
2.5
2.5
2.5
2.5
3.0
3.0
3.0
4.0
4.0
4.0
Minimum pulse width for clear (2)
and preset
tODH
Output data hold time after
clock
C1 = 35 pF (3)
1.0
1.0
1.0
1.0
ns
tCNT
fCNT
Minimum global clock period
5.7
5.7
7.1
7.1
8.0
8.0
10.0
10.0
ns
Maximum internal global clock (4)
frequency
175.4
140.8
125.0
100.0
MHz
tACNT
fACNT
Minimum array clock period
ns
Maximum internal array clock (4)
frequency
175.4
250.0
140.8
200.0
125.0
166.7
100.0
125.0
MHz
fMAX
Maximum clock frequency
(5)
MHz
Table 27. EPM7064S Internal Timing Parameters (Part 1 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
-6 -7
Min Max Min Max Min Max Min Max
Unit
-5
-10
tIN
Input pad and buffer delay
I/O input pad and buffer delay
Fast input delay
0.2
0.2
2.2
3.1
0.9
2.6
2.5
0.7
0.2
0.7
5.2
4.0
4.5
9.0
4.0
0.2
0.2
2.6
3.8
1.1
3.2
3.2
0.8
0.3
0.8
5.3
4.0
4.5
9.0
4.0
0.5
0.5
1.0
4.0
0.8
3.0
3.0
2.0
2.0
2.5
7.0
4.0
4.5
9.0
4.0
0.5
0.5
1.0
5.0
0.8
5.0
5.0
2.0
1.5
2.0
5.5
5.0
5.5
9.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
tFIN
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
tOD2
tOD3
tZX1
tZX2
tZX3
tXZ
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad delay C1 = 35 pF
Output buffer and pad delay C1 = 35 pF (6)
Output buffer and pad delay C1 = 35 pF
Output buffer enable delay
Output buffer enable delay
Output buffer enable delay
Output buffer disable delay
Register setup time
C1 = 35 pF
C1 = 35 pF (6)
C1 = 35 pF
C1 = 5 pF
tSU
0.8
1.0
3.0
2.0
Altera Corporation
39
ALTERA [ ALTERA CORPORATION ]
