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EPM7192SQC160-10 参数 Datasheet PDF下载

EPM7192SQC160-10图片预览
型号: EPM7192SQC160-10
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程逻辑器件系列 [Programmable Logic Device Family]
分类和应用: 可编程逻辑器件输入元件LTE时钟
文件页数/大小: 62 页 / 1087 K
品牌: ALTERA [ ALTERA CORPORATION ]
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MAX 7000 Programmable Logic Device Family Data Sheet  
Table 27. EPM7064S Internal Timing Parameters (Part 2 of 2)  
Note (1)  
Symbol  
Parameter  
Conditions  
Speed Grade  
-6 -7  
Min Max Min Max Min Max Min Max  
Unit  
-5  
-10  
tH  
Register hold time  
1.7  
1.9  
2.0  
1.8  
2.0  
3.0  
3.0  
3.0  
ns  
ns  
tFSU  
Register setup time of fast  
input  
tFH  
Register hold time of fast  
input  
0.6  
0.7  
0.5  
0.5  
ns  
tRD  
Register delay  
1.2  
0.9  
2.7  
2.6  
1.6  
2.0  
2.0  
1.1  
12.0  
1.6  
1.0  
3.3  
3.2  
1.9  
2.4  
2.4  
1.3  
11.0  
1.0  
1.0  
3.0  
3.0  
1.0  
2.0  
2.0  
1.0  
10.0  
2.0  
2.0  
5.0  
5.0  
1.0  
3.0  
3.0  
1.0  
11.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCOMB  
tIC  
Combinatorial delay  
Array clock delay  
Register enable time  
Global control delay  
Register preset time  
Register clear time  
PIA delay  
tEN  
tGLOB  
tPRE  
tCLR  
tPIA  
(7)  
(8)  
tLPA  
Low-power adder  
Notes to tables:  
(1) These values are specified under the recommended operating conditions shown in Table 11. See Figure 13 for more  
information on switching waveforms.  
(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The t  
parameter  
LPA  
must be added to this minimum width if the clear or reset signal incorporates the t  
parameter into the signal  
LAD  
path.  
(3) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This  
parameter applies for both global and array clocking.  
(4) These parameters are measured with a 16-bit loadable, enabled, up/ down counter programmed into each LAB.  
(5) The f  
values represent the highest frequency for pipelined data.  
MAX  
(6) Operating conditions: V  
= 3.3 V ± 10% for commercial and industrial use.  
CCIO  
(7) For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,  
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these  
devices, add an additional 0.1 ns to the PIA timing value.  
(8) The t  
parameter must be added to the t  
, t  
, t , t , t  
, t  
, and t parameters for macrocells  
LPA  
LAD LAC IC EN SEXP ACL  
CPPW  
running in the low-power mode.  
40  
Altera Corporation  
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